hal_h8s_h8s2674.cdl

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

# ====================================================================
#
#      hal_h8s_h8s2674.cdl
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#      H8S/2674 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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## eCos is free software; you can redistribute it and/or modify it under
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## You should have received a copy of the GNU General Public License along
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## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
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## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s):      ysato
# Original data:  nickg
# Contributors:   ysato, Uwe Kindler
# Date:           2003-12-06
#
#####DESCRIPTIONEND####
#
# ====================================================================

cdl_package CYGPKG_HAL_H8S_H8S2674 {
    display "H8S/2674 variant"
    parent        CYGPKG_HAL_H8S
    implements    CYGINT_HAL_H8S_VARIANT
    implements    CYGHWR_HAL_H8S_CPU_2600
    implements    CYGINT_HAL_TESTS_NO_CACHES
    hardware   
    include_dir   cyg/hal
    define_header hal_h8s_h8s2674.h
    description   "
           The H8S/2674 variant HAL package provides generic support for the 
           H8S/2674 processor. It is also necessary to select a specific target 
           platform HAL package."

    define_proc {
        puts $::cdl_header "#include <pkgconf/hal_h8s.h>"
    }

    compile       var_misc.c var_intr.S
    
    cdl_option CYGBLD_HAL_H8S_WATCHDOG_INTERRUPT_CODE {
        display "Watchdog module mask, unmask, ackn. support"
        default_value    0
        description  "
            Watchdog module interrupt mask, unmask and acknowledge differs 
            from other H8S/2674 modules. In order to support the function 
            cyg_interrupt_mask, cyg_interrupt_unmask and cyg_interrupt_acknowledge 
            for the watchdog module (also if you use it as a simple overflow timer), 
            additional code is necessary that is executet everytime one of 
            the functions above is called. If you don't need the module or if you 
            use the eCos H8S/2674 watchdog driver then you do not need this extra 
            code. This will save some time in ISR's and decrease code size a 
            little bit."
    }
    
    cdl_component CYGHWR_HAL_H8S_CLOCK_SETTINGS {
        display          "On-Chip generic clock controls"
        description      "
            The various clocks used by the system are controlled by
            these options, some of which are derived from platform
            settings."
        flavor        none
        no_define
        
        cdl_option CYGHWR_HAL_H8S_MULT_RATE {
 	    display	     "PLL Multiplier Rate (Nx)"
 	    flavor	     data
            legal_values     { 1 2 4 }
 	    default_value    1
 	    description	     "
               The PLL circuit has the function of multiplying the frequency
               of the clock from the oscillator by a factor of 1, 2, or 4."
 	}
 	
 	cdl_option CYGHWR_HAL_H8S_DIVIDER_RATE {
 	    display	     "Clock Divider Rate (1/n)"
 	    flavor	     data
            legal_values     { 1 2 4 8 16 32 }
 	    default_value    1
 	    description	     "
               The frequency divider divides the PLL output clock to 
               generate a 1/2, 1/4, 1/8, 1/16, or 1/32 clock. 
               The following points should be noted since the frequency of 
               clock changes according to the setting of Clock Divider Rate and 
               PLL Multiplier Rate. Select the clock division ratio that is within 
               the operation guaranteed range of clock cycle time tcyc shown in 
               the AC timing of Electrical Characteristics. In other words, the 
               range of clock must be specified from 8 MHz (min) to 33 MHz (max). 
               Outside of this range must be prevented. All the on-chip peripheral 
               modules operate on the clock. Therefore, note that the time processing
               of modules such as a timer and SCI differ before and after changing 
               the clock division ratio. In addition, wait time for clearing software 
               standby mode differs by changing the clock division ratio. See the 
               description, Setting Oscillation Stabilization Time after Clearing Software
               Standby Mode in section 22.2.3, Software Standby Mode, of the H8S2674
               hardware manual for details."
 	}
 	
        cdl_option CYGHWR_HAL_H8S_INTERNAL_MODULE_CLOCK {
             display          "Internal clock to peripheral modules (Hz)"
             flavor           data
             legal_values     8000000 to 33000000
             calculated       { CYGHWR_HAL_H8S_CPG_INPUT * CYGHWR_HAL_H8S_MULT_RATE / CYGHWR_HAL_H8S_DIVIDER_RATE}
             description      "
                 The on chip peripheral modules operate on the system clock.
                 The system clock (core CPU speed) is computed from the input clock 
                 speed,  (OSC/Clock Frequency in platform hal) the PLL Multiplier Rate 
                 and the Divider Rate. (Core CPU speed = OSC/Clock Frequency * PLL 
                 Multiplier Rate / Divider Rate). Select the clock division ratio 
                 that is within the operation guaranteed range of clock cycle time 
                 tcyc shown in the AC timing of Electrical Characteristics. In other 
                 words, the range of clock must be specified from 8 MHz (min) to 
                 33 MHz (max). Outside of this range must be prevented."
         }
    }
    
    cdl_component CYGPKG_HAL_H8S_H8S2674_OPTIONS {
        display "H8S/2674 build options"
        flavor  none
        description   "
	    Package specific build options including control over
	    compiler flags used only in building this package,
	    and details of which tests are built."
    
        cdl_option CYGPKG_HAL_H8S_H8S2674_TESTS {
            display "H8S/2674 tests"
            flavor  data
            no_define
            calculated { 
                 ""
                 . ((CYGPKG_KERNEL) ? "tests/h8s_except1 tests/h8s_intr0" : "")
                 . ((CYGFUN_KERNEL_API_C) ? " tests/h8s_kexcept1 tests/h8s_kintr0 tests/intnest" : "")
            }
            description   "
                This option specifies the set of tests for the H8S/2674 variant."
        }
    }
}