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📄 mod_regs_pio.h

📁 ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html
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#ifndef CYGONCE_MOD_REGS_PIO_H
#define CYGONCE_MOD_REGS_PIO_H

//==========================================================================
//
//      mod_regs_pio.h
//
//      I/O Port Controler Register
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Uwe Kindler
// Contributors: Uwe Kindler
// Date:         2004-11-03
//              
//####DESCRIPTIONEND####
//
//==========================================================================


//==========================================================================
//                            DOXYGEN FILE HEADER
/// \file    mod_regs_pio.h
/// \brief   I/O Port Controler Register.
/// \author  Uwe Kindler
/// \date    2004-11-03
//==========================================================================

//==========================================================================
//                           REGISTER ADDRESSES
//==========================================================================

//--------------------------------------------------------------------------
//              I/O PORTS DATA DIRECTION REGISTERS (DDR)
//
#define CYGARC_P1DDR   0xFFFE30
#define CYGARC_P3DDR   0xFFFE32
#define CYGARC_PADDR   0xFFFE39
#define CYGARC_PBDDR   0xFFFE3A
#define CYGARC_PCDDR   0xFFFE3B
#define CYGARC_PDDDR   0xFFFE3C
#define CYGARC_PEDDR   0xFFFE3D
#define CYGARC_PFDDR   0xFFFE3E
#define CYGARC_PHDDR   0xFFFC20
#define CYGARC_PJDDR   0xFFFC21


//--------------------------------------------------------------------------
//                        PULL UP MOS CONTROL REGISTERS
//
#define CYGARC_PAPCR   0xFFFE40
#define CYGARC_PBPCR   0xFFFE41
#define CYGARC_PCPCR   0xFFFE42
#define CYGARC_PDPCR   0xFFFE43
#define CYGARC_PEPCR   0xFFFE44


//--------------------------------------------------------------------------
//                        OPEN DRAIN CONTROL REGSITERS
//
#define CYGARC_P3ODR   0xFFFE46
#define CYGARC_PAODR   0xFFFE47
#define CYGARC_PBODR   0xFFFE48
#define CYGARC_PCODR   0xFFFE49


//--------------------------------------------------------------------------
//                              DATA REGISTERS
//
#define CYGARC_P1DR    0xFFFF00
#define CYGARC_P3DR    0xFFFF02
#define CYGARC_PADR    0xFFFF09
#define CYGARC_PBDR    0xFFFF0A
#define CYGARC_PCDR    0xFFFF0B
#define CYGARC_PDDR    0xFFFF0C
#define CYGARC_PEDR    0xFFFF0D
#define CYGARC_PFDR    0xFFFF0E
#define CYGARC_PHDR    0xFFFC24
#define CYGARC_PJDR    0xFFFC25



//--------------------------------------------------------------------------
//                               PORTS REGISTERS
//
#define CYGARC_PORT1   0xFFFFB0
#define CYGARC_PORT3   0xFFFFB2
#define CYGARC_PORT4   0xFFFFB3
#define CYGARC_PORT5   0xFFFFB8
#define CYGARC_PORTA   0xFFFFB9
#define CYGARC_PORTB   0xFFFFBA
#define CYGARC_PORTC   0xFFFFBB
#define CYGARC_PORTD   0xFFFFBC
#define CYGARC_PORTE   0xFFFFBD
#define CYGARC_PORTF   0xFFFFBE
#define CYGARC_PORTH   0xFFFC28
#define CYGARC_PORTJ   0xFFFC29


#ifndef __ASSEMBLER__
//==========================================================================
//                           REGISTER STRUCTURE
//==========================================================================
struct st_p1 {                                          // struct P1    
             unsigned char      DDR;                    // P1DDR        
             char               wk1[207];               //              
             union {                                    // P1DR         
                   unsigned char BYTE;                  //  Byte Access 
                   struct {                             //  Bit  Access 
                          unsigned char B7:1;           //    Bit 7     
                          unsigned char B6:1;           //    Bit 6     
                          unsigned char B5:1;           //    Bit 5     
                          unsigned char B4:1;           //    Bit 4     
                          unsigned char B3:1;           //    Bit 3     
                          unsigned char B2:1;           //    Bit 2     
                          unsigned char B1:1;           //    Bit 1     
                          unsigned char B0:1;           //    Bit 0     
                          }      BIT;                   //              
                   }            DR;                     //              
             char               wk2[175];               //              
             union {                                    // P1PORT       
                   unsigned char BYTE;                  //  Byte Access 
                   struct {                             //  Bit  Access 
                          unsigned char B7:1;           //    Bit 7     
                          unsigned char B6:1;           //    Bit 6     
                          unsigned char B5:1;           //    Bit 5     
                          unsigned char B4:1;           //    Bit 4     
                          unsigned char B3:1;           //    Bit 3     
                          unsigned char B2:1;           //    Bit 2     
                          unsigned char B1:1;           //    Bit 1     
                          unsigned char B0:1;           //    Bit 0     
                          }      BIT;                   //              
                   }            PORT;                   //              
};                                                      //              
struct st_p3 {                                          // struct P3    
             unsigned char      DDR;                    // P3DDR        
             char               wk1[19];                //              
             union {                                    // P3ODR        
                   unsigned char BYTE;                  //  Byte Access 
                   struct {                             //  Bit  Access 
                          unsigned char   :2;           //              
                          unsigned char B5:1;           //    Bit 5     
                          unsigned char B4:1;           //    Bit 4     
                          unsigned char B3:1;           //    Bit 3     
                          unsigned char B2:1;           //    Bit 2     
                          unsigned char B1:1;           //    Bit 1     
                          unsigned char B0:1;           //    Bit 0     
                          }      BIT;                   //              
                   }            ODR;                    //              
             char               wk2[187];               //              
             union {                                    // P3DR         
                   unsigned char BYTE;                  //  Byte Access 
                   struct {                             //  Bit  Access 
                          unsigned char   :2;           //              
                          unsigned char B5:1;           //    Bit 5     
                          unsigned char B4:1;           //    Bit 4     
                          unsigned char B3:1;           //    Bit 3     
                          unsigned char B2:1;           //    Bit 2     
                          unsigned char B1:1;           //    Bit 1     
                          unsigned char B0:1;           //    Bit 0     
                          }      BIT;                   //              
                   }            DR;                     //              
             char               wk3[175];               //              
             union {                                    // P3PORT       
                   unsigned char BYTE;                  //  Byte Access 
                   struct {                             //  Bit  Access 
                          unsigned char   :2;           //              
                          unsigned char B5:1;           //    Bit 5     

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