📄 mod_regs_intc.h
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#ifndef CYGONCE_MOD_REGS_INTC_H
#define CYGONCE_MOD_REGS_INTC_H
//==========================================================================
//
// mod_regs_intc.h
//
// Interrupt Controler Register
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Uwe Kindler
// Contributors: Uwe Kindler
// Date: 2004-11-02
//
//####DESCRIPTIONEND####
//
//==========================================================================
//==========================================================================
// DOXYGEN FILE HEADER
/// \file mod_regs_intc.h
/// \brief Interrupt Controller Register definitions.
/// \author Uwe Kindler
/// \date 2004-11-02
//==========================================================================
//==========================================================================
// REGISTER ADDRESSES
//==========================================================================
//--------------------------------------------------------------------------
// interrupt priority registers
//
#define CYGARC_IPRA 0xFFFEC0
#define CYGARC_IPRB 0xFFFEC1
#define CYGARC_IPRC 0xFFFEC2
#define CYGARC_IPRD 0xFFFEC3
#define CYGARC_IPRE 0xFFFEC4
#define CYGARC_IPRF 0xFFFEC5
#define CYGARC_IPRG 0xFFFEC6
#define CYGARC_IPRH 0xFFFEC7
#define CYGARC_IPRJ 0xFFFEC9
#define CYGARC_IPRK 0xFFFECA
#define CYGARC_IPRL 0xFFFECB
#define CYGARC_IPRM 0xFFFECC
//--------------------------------------------------------------------------
// interrupt registers
//
#define CYGARC_ISCRH 0xFFFE12
#define CYGARC_ISCRL 0xFFFE13
#define CYGARC_IER 0xFFFE14
#define CYGARC_ISR 0xFFFE15
#ifndef __ASSEMBLER__
//==========================================================================
// REGISTER STRUCTURE
//==========================================================================
struct st_intc { // struct INTC
union { // ISCR
unsigned int WORD; // Word Access
struct { // Byte Access
unsigned char H; // ISCRH
unsigned char L; // ISCRL
} BYTE; //
struct { // Bit Access
unsigned char :4; //
unsigned char IRQ5SC:2; // IRQ5SC
unsigned char IRQ4SC:2; // IRQ4SC
unsigned char IRQ3SC:2; // IRQ3SC
unsigned char IRQ2SC:2; // IRQ2SC
unsigned char IRQ1SC:2; // IRQ1SC
unsigned char IRQ0SC:2; // IRQ0SC
} BIT; //
} ISCR; //
union { // IER
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :2; //
unsigned char IRQ5E:1; // IRQ5E
unsigned char IRQ4E:1; // IRQ4E
unsigned char IRQ3E:1; // IRQ3E
unsigned char IRQ2E:1; // IRQ2E
unsigned char IRQ1E:1; // IRQ1E
unsigned char IRQ0E:1; // IRQ0E
} BIT; //
} IER; //
union { // ISR
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :2; //
unsigned char IRQ5F:1; // IRQ5F
unsigned char IRQ4F:1; // IRQ4F
unsigned char IRQ3F:1; // IRQ3F
unsigned char IRQ2F:1; // IRQ2F
unsigned char IRQ1F:1; // IRQ1F
unsigned char IRQ0F:1; // IRQ0F
} BIT; //
} ISR; //
char wk1[170]; //
union { // IPRA
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _IRQ0:3; // IRQ0
unsigned char :1; //
unsigned char _IRQ1:3; // IRQ1
} BIT; //
} IPRA; //
union { // IPRB
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _IRQ23:3; // IRQ2,IRQ3
unsigned char :1; //
unsigned char _IRQ45:3; // IRQ4,IRQ5
} BIT; //
} IPRB; //
union { // IPRC
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :5; //
unsigned char _DTC:3; // DTC
} BIT; //
} IPRC; //
union { // IPRD
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _WDT0:3; // WDT0
} BIT; //
} IPRD; //
union { // IPRE
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _PBC:3; // PBC
unsigned char :1; //
unsigned char _AD :3; // A/D,WDT1
} BIT; //
} IPRE; //
union { // IPRF
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _TPU0:3; // TPU0
unsigned char :1; //
unsigned char _TPU1:3; // TPU1
} BIT; //
} IPRF; //
union { // IPRG
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _TPU2:3; // TPU2
unsigned char :1; //
unsigned char _TPU3:3; // TPU3
} BIT; //
} IPRG; //
union { // IPRH
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _TPU4:3; // TPU4
unsigned char :1; //
unsigned char _TPU5:3; // TPU5
} BIT; //
} IPRH; //
char wk2; //
union { // IPRJ
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :5; //
unsigned char _SCI0:3; // SCI0
} BIT; //
} IPRJ; //
union { // IPRK
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _SCI1:3; // SCI1
unsigned char :1; //
unsigned char _SCI2:3; // SCI2
} BIT; //
} IPRK; //
union { // IPRL
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :5; //
unsigned char _IIC:3; // IIC
} BIT; //
} IPRL; //
union { // IPRM
unsigned char BYTE; // Byte Access
struct { // Bit Access
unsigned char :1; //
unsigned char _HCAN1:3; // PWM,HCAN1
unsigned char :1; //
unsigned char _HCAN0:3; // HCAN0
} BIT; //
} IPRM; //
};
//==========================================================================
// STRUCTURED REGISTER ACCESS
//==========================================================================
#define HAL_H8S_REG_INTC (*(volatile struct st_intc *)0xFFFE12) // INTC Address
#endif //#ifndef __ASSEMBLER__
//--------------------------------------------------------------------------
#endif // CYGONCE_MOD_REGS_INTC_H
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