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📄 hal_h8s_h8s2638.cdl

📁 ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html
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# ====================================================================
#
#      hal_h8s_h8s2674.cdl
#
#      H8S/2674 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s):      ysato
# Original data:  nickg
# Contributors:   ysato, Uwe Kindler
# Date:           2003-12-06
#
#####DESCRIPTIONEND####
#
# ====================================================================

cdl_package CYGPKG_HAL_H8S_H8S2638 {
    display "H8S/2638 variant"
    parent        CYGPKG_HAL_H8S
    implements    CYGINT_HAL_H8S_VARIANT
    implements    CYGHWR_HAL_H8S_CPU_2600
    implements    CYGINT_HAL_TESTS_NO_CACHES
    hardware   
    include_dir   cyg/hal
    define_header hal_h8s_h8s2638.h
    description   "
           The H8S/2638 variant HAL package provides generic support for the 
           H8S/2638 processor. It is also necessary to select a specific target 
           platform HAL package."

    define_proc {
        puts $::cdl_header "#include <pkgconf/hal_h8s.h>"
    }

    compile       var_misc.c var_intr.S
    
   
    cdl_component CYGHWR_HAL_H8S_CLOCK_SETTINGS {
        display          "On-Chip generic clock controls"
        description      "
            The various clocks used by the system are controlled by
            these options, some of which are derived from platform
            settings."
        flavor        none
        no_define
        
        cdl_option CYGHWR_HAL_H8S_MULT_RATE {
 	    display	     "PLL Multiplier Rate (Nx)"
 	    flavor	     data
            legal_values     { 1 2 4 }
 	    default_value    1
 	    description	     "
               The PLL circuit has the function of multiplying the frequency
               of the clock from the oscillator by a factor of 1, 2, or 4.
               A system clock frequency multiplied by the multiplication factor
               should not exceed the maximum operating frequency of 20 MHz."
 	    }
 	
        cdl_option CYGHWR_HAL_H8S_INTERNAL_MODULE_CLOCK {
             display          "Internal clock to peripheral modules (Hz)"
             flavor           data
             legal_values     8000000 to 20000000
             calculated       { CYGHWR_HAL_H8S_CPG_INPUT * CYGHWR_HAL_H8S_MULT_RATE}
             description      "
                 The on chip peripheral modules operate on the system clock.
                 The system clock (core CPU speed) is computed from the input clock 
                 speed,  (OSC/Clock Frequency in platform hal) and the PLL Multiplier 
                 Rate. (Core CPU speed = OSC/Clock Frequency * PLL Multiplier Rate). 
                 Select the clock division ratio. The range of clock must be specified 
                 from 8 MHz (min) to 20 MHz (max). Outside of this range must be 
                 prevented."
         }
    }
    
    cdl_component CYGPKG_HAL_H8S_H8S2638_OPTIONS {
        display "H8S/2638 build options"
        flavor  none
        description   "
	    Package specific build options including control over
	    compiler flags used only in building this package,
	    and details of which tests are built."
    
        cdl_option CYGPKG_HAL_H8S_H8S2638_TESTS {
            display "H8S/2638 tests"
            flavor  data
            no_define
            calculated { 
                 ""
                 . ((CYGPKG_KERNEL) ? "tests/h8s_except1 tests/h8s_intr0" : "")
                 . ((CYGFUN_KERNEL_API_C) ? " tests/h8s_kexcept1 tests/h8s_kintr0 tests/intnest" : "")
            }
            description   "
                This option specifies the set of tests for the H8S/2674 variant."
        }
    }
}

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