vectors.s

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

//=============================================================================
//
//  vectors.S
//
//  H8S exception vectors
//
//=============================================================================
//###ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//###ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Yoshinori Sato
// Contributors: Yoshinori Sato, Uwe Kindler
// Date:         2003-12-06
// Purpose:      H8S exception vectors
// Description: This file defines the code placed into the exception
//              vectors. It also contains the first level default VSRs
//              that save and restore state for both exceptions and
//              interrupts.
//
//####DESCRIPTIONEND####
//
//=============================================================================


//=============================================================================
//                            DOXYGEN FILE HEADER
/// \file    vectors.S
/// \brief   H8S exception vectors and startup code.
/// \author  Yoshinori Sato, Uwe Kindler
/// \date    2003-12-06
///
/// This file defines the code placed into the exception vectors. It also 
/// contains the first level default VSRs that save and restore state for 
/// both exceptions and interrupts.
//=============================================================================


//=============================================================================
//                                     INCLUDES
//=============================================================================
#include <pkgconf/hal.h>

#ifdef CYGPKG_REDBOOT
  #include <pkgconf/redboot.h>
#endif
    
#ifdef CYGPKG_KERNEL
  #include <pkgconf/kernel.h>   
#endif      

#include <cyg/hal/basetype.h>   
#include <cyg/hal/var_intr_numbers.h>
#include <cyg/hal/arch.inc> 
#include <cyg/hal/variant.inc>



//=============================================================================
//                            ASSEMBLER SETTINGS
//=============================================================================
    .h8300s
            
    
//=============================================================================
//                               ROM VECTOR TABLE 
// DESCRIPTION:
//     This is the H8S ROM vector table. This table is located at address
//     0x00 in memory. It contains 128 entries of 4 bytes each entry. The
//     vector table contains addresses of the next instructions to be executed
//
// NOTES: 
//     Because this vector table is locted in ROM we use an additional 
//     interrupt hook table in RAM so that it is possible to attach new
//     interrupt service routines if we build an RAM application or during
//     runtime. Each entry of the ROM vector table is filled with the address 
//     of the associated interrupt hook vector - so if an exception/interrupt
//     occurs we immeadiately go into the interrupt hook table.
//
//     We build this table only if we use ROM starup or if we encode for
//     simulator.
//============================================================================= 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)   
    .section .vects,"a"
    .global   reset_vector

__rom_int_vect_tbl:
reset_vector:
    .long   CYG_LABEL_DEFN(_start)      // Power on reset
    .long   CYG_LABEL_DEFN(_start)      // Manual reset
    .long   _svect2                     // Vector 2-4 reserved for system use
    .long   _svect3                
    .long   _svect4
    .long   _svect5                     // Trace
    .long   _svect6
    .long   _svect7
    .long   _svect8
    .long   _svect9
    .long   _svect10
    .long   _svect11
    .long   _svect12
    .long   _svect13
    .long   _svect14
    .long   _svect15
    .long   _svect16
    .long   _svect17
    .long   _svect18
    .long   _svect19
    .long   _svect20
    .long   _svect21
    .long   _svect22
    .long   _svect23
    .long   _svect24
    .long   _svect25
    .long   _svect26
    .long   _svect27
    .long   _svect28
    .long   _svect29
    .long   _svect30
    .long   _svect31
    .long   _svect32
    .long   _svect33
    .long   _svect34
    .long   _svect35
    .long   _svect36
    .long   _svect37
    .long   _svect38
    .long   _svect39
    .long   _svect40
    .long   _svect41
    .long   _svect42
    .long   _svect43
    .long   _svect44
    .long   _svect45
    .long   _svect46
    .long   _svect47
    .long   _svect48
    .long   _svect49
    .long   _svect50
    .long   _svect51
    .long   _svect52
    .long   _svect53
    .long   _svect54
    .long   _svect55
    .long   _svect56
    .long   _svect57
    .long   _svect58
    .long   _svect59
    .long   _svect60
    .long   _svect61
    .long   _svect62
    .long   _svect63
    .long   _svect64
    .long   _svect65
    .long   _svect66
    .long   _svect67
    .long   _svect68
    .long   _svect69
    .long   _svect70
    .long   _svect71
    .long   _svect72
    .long   _svect73
    .long   _svect74
    .long   _svect75
    .long   _svect76
    .long   _svect77
    .long   _svect78
    .long   _svect79
    .long   _svect80
    .long   _svect81
    .long   _svect82
    .long   _svect83
    .long   _svect84
    .long   _svect85
    .long   _svect86
    .long   _svect87
    .long   _svect88
    .long   _svect89
    .long   _svect90
    .long   _svect91
    .long   _svect92
    .long   _svect93
    .long   _svect94
    .long   _svect95
    .long   _svect96
    .long   _svect97
    .long   _svect98
    .long   _svect99
    .long   _svect100
    .long   _svect101
    .long   _svect102
    .long   _svect103
    .long   _svect104
    .long   _svect105
    .long   _svect106
    .long   _svect107
    .long   _svect108
    .long   _svect109
    .long   _svect110
    .long   _svect111
    .long   _svect112
    .long   _svect113
    .long   _svect114
    .long   _svect115
    .long   _svect116
    .long   _svect117
    .long   _svect118
    .long   _svect119
    .long   _svect120
    .long   _svect121
    .long   _svect122
    .long   _svect123
    .long   _svect124
    .long   _svect125
    .long   _svect126
    .long   _svect127
#endif // End of #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)

                  
//=============================================================================
//                       RAM INTERRUPT SHADOW VECTOR TABLE
// DESCRIPTION:
//     This is the interrupt shadow vector table to be placed in RAM. We come 
//     into this table directly from the ROM vector table. Here we jump to
//     'interrupt_entry' routine where fourther processing takes place.
//     We use jsr because we need an valid PC on stack for interrupt number
//     calculation. Each entry requires 8 bytes because we place two
//     instructions in the table:
//         1. orc #7, exr                  = 4 Bytes
//         2. jsr @interrupt_entry         = 4 Bytes
//
//     We have to mask all interrupt in exr because in ICM2 only interrupts
//     with the same or lower priority than the current interrupt will be 
//     masked. 
//
// NOTES:
//     If we are in interrupt control mode 2 then an interrupt will mask only
//     interrupts of the same or lower priority than the priority of the
//     interrupt just occured. Therfore the first instruction after 
//     interrupt occurence is disabling of all interrupts by an ORC instruction
//=============================================================================

//=-----------------------------------------------------------------------------
// This macro defines one entry into interrupt shadow vector table
//
    .macro SVECT_TBL_ENTRY no
    _svect\no: jsr @interrupt_entry        
    .endm 

//=-----------------------------------------------------------------------------
// This is the real shadow vector table. Each entry is 4 byte long because
// jsr instruction requires 4 bytes memory. We use the above defined macro to 
// create the following table. The size of the table is equal to the harware
// vector table size - 512 bytes
//
// _svect0: jsr @interrupt_entry
// _svect1: jsr @interrupt_entry
// _svect2: jsr @interrupt_entry
//          
// ...
//
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)   
  .section .svects,"ax"
__ram_int_svect_tbl:
SVECT_TBL_ENTRY 0     // we never come here but we define the first
SVECT_TBL_ENTRY 1     // two entries in order to have a defined state here
SVECT_TBL_ENTRY 2     
SVECT_TBL_ENTRY 3
SVECT_TBL_ENTRY 4
SVECT_TBL_ENTRY 5
SVECT_TBL_ENTRY 6
SVECT_TBL_ENTRY 7
SVECT_TBL_ENTRY 8
SVECT_TBL_ENTRY 9
SVECT_TBL_ENTRY 10    
SVECT_TBL_ENTRY 11
SVECT_TBL_ENTRY 12    
SVECT_TBL_ENTRY 13
SVECT_TBL_ENTRY 14
SVECT_TBL_ENTRY 15
SVECT_TBL_ENTRY 16
SVECT_TBL_ENTRY 17
SVECT_TBL_ENTRY 18
SVECT_TBL_ENTRY 19
SVECT_TBL_ENTRY 20    
SVECT_TBL_ENTRY 21
SVECT_TBL_ENTRY 22    
SVECT_TBL_ENTRY 23
SVECT_TBL_ENTRY 24
SVECT_TBL_ENTRY 25
SVECT_TBL_ENTRY 26
SVECT_TBL_ENTRY 27
SVECT_TBL_ENTRY 28
SVECT_TBL_ENTRY 29
SVECT_TBL_ENTRY 30    
SVECT_TBL_ENTRY 31
SVECT_TBL_ENTRY 32    
SVECT_TBL_ENTRY 33
SVECT_TBL_ENTRY 34
SVECT_TBL_ENTRY 35
SVECT_TBL_ENTRY 36
SVECT_TBL_ENTRY 37
SVECT_TBL_ENTRY 38
SVECT_TBL_ENTRY 39
SVECT_TBL_ENTRY 40    
SVECT_TBL_ENTRY 41
SVECT_TBL_ENTRY 42    
SVECT_TBL_ENTRY 43
SVECT_TBL_ENTRY 44
SVECT_TBL_ENTRY 45
SVECT_TBL_ENTRY 46
SVECT_TBL_ENTRY 47
SVECT_TBL_ENTRY 48
SVECT_TBL_ENTRY 49
SVECT_TBL_ENTRY 50    
SVECT_TBL_ENTRY 51
SVECT_TBL_ENTRY 52    
SVECT_TBL_ENTRY 53
SVECT_TBL_ENTRY 54
SVECT_TBL_ENTRY 55
SVECT_TBL_ENTRY 56
SVECT_TBL_ENTRY 57
SVECT_TBL_ENTRY 58
SVECT_TBL_ENTRY 59
SVECT_TBL_ENTRY 60    
SVECT_TBL_ENTRY 61
SVECT_TBL_ENTRY 62    
SVECT_TBL_ENTRY 63
SVECT_TBL_ENTRY 64
SVECT_TBL_ENTRY 65