arch.inc

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

#ifndef CYGONCE_HAL_ARCH_INC
#define CYGONCE_HAL_ARCH_INC
//=============================================================================
//
//  arch.inc
//
//  H8S assembler header file
//
//=============================================================================
//###ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//###ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):       yoshinori sato
// Contributors:    yoshinori sato, Uwe Kindler
// Date:            2003-12-02
// Purpose:         Architecture definitions.
// Description:     This file contains various definitions and macros that are
//                  useful for writing assembly code for the H8S CPU family.
// Usage:
//      #include <cyg/hal/arch.inc>
//      ...
//      
//
//####DESCRIPTIONEND####
//
//=============================================================================


//=============================================================================
//                                   INCLUDES
//=============================================================================
#include <pkgconf/hal.h>
#include <cyg/hal/variant.inc>


//=============================================================================
//                                     DEFINES
//=============================================================================
//
// Register Sizes
//
#define SIZE_EXR     2
#define SIZE_PC_CCR  4
#define SIZE_PC      4
#define SIZE_SP      4
#define SIZE_MACL    4
#define SIZE_MACH    4
#define SIZE_MAC     8
#define SIZE_ER0_ER6 (7*4)
#define SIZE_ER0_ER7 (8*4)

//
// if we store MAC register then the saved state contains the additional 8 bytes
// of the MAC register
//
#if defined(CYGHWR_HAL_H8S_USE_MAC)
  #define SIZE_SAVED_STATE (SIZE_PC_CCR + SIZE_EXR + SIZE_ER0_ER7 + SIZE_MAC)
  //
  // this defines the location of several registers in saved machine state
  // on stack - this is required for adressing in assembler code
  //
  #define SAVED_STATE_SP   (SIZE_ER0_ER6 + SIZE_MAC)
  #define SAVED_STATE_PC   (SIZE_ER0_ER7 + SIZE_MAC + SIZE_EXR)
  //
  // saves MAC register on stack - do not use er0 or er1 here because these
  // macros are used in context switch code and er0,er1 contain
  //
  .macro hal_push_mac
   stmac   macl, er2                              
   stmac   mach, er3                             
   stm.l   er2 - er3, @ - sp           // push MACL-MACH
  .endm
  //
  // restores MAC from stack
  //
  .macro hal_pop_mac
   ldm.l    @sp+, er2 - er3            // pop MACL-MACH         
   ldmac    er3, mach
   ldmac    er2, macl
  .endm
#else
  #define SIZE_SAVED_STATE (SIZE_PC_CCR + SIZE_EXR + SIZE_ER0_ER7)
  //
  // this defines the location of several registers in saved machine state
  // on stack - this is required for adressing in assembler code
  //
  #define SAVED_STATE_SP    SIZE_ER0_ER6
  #define SAVED_STATE_PC   (SIZE_ER0_ER7 + SIZE_EXR)
  //
  // the following macros are empty here because we do not use  MAC register
  //
  .macro hal_push_mac
  .endm
   
  .macro hal_pop_mac
  .endm
#endif 


//=============================================================================
//                              CPU SPECIFIC MACROS 
// DESCRIPTION:
//     These provide a common assembler interface to operations that may 
//     have CPU specific implementations on different variants of the
//     architecture.
//=============================================================================     


//=============================================================================
//                                    CPU INIT  
// DESCRIPTION:
//     Initialize CPU status registers. Most importantly, the CPU interrupt 
//     mask is set to disable interrupts.
//============================================================================= 
#ifndef CYGPKG_HAL_H8S_CPU_INIT_DEFINED
#define CYGPKG_HAL_H8S_CPU_INIT_DEFINED
    .macro  hal_cpu_init
    ldc #0x80, ccr           // mask I bit in CCR
    ldc #0x07, exr           // mask I0-I2 bits in EXR and disable trace
    .endm
#endif
    //
    // Enable further exception processing, and disable
    // interrupt processing.
    //
    .macro hal_cpu_except_enable
    .endm           
    //
    // Return from exception.
    //
    .macro  hal_cpu_eret pc,sr
    .endm


//=============================================================================
//                            INTERRUPT CONTROLLER INIT 
// DESCRIPTION:
//     Initialize interrupt controller. At the very least, it should be 
//     configured to mask all interrupts. It may also be necessary to set up 
//     the mapping from the interrupt controller抯 vector number space to the 
//     CPU抯 exception number space. Similar mappings may need to be set up
//     between primary and secondary interrupt controllers.
//=============================================================================
#ifndef CYGPKG_HAL_H8S_INTC_DEFINED

#ifndef CYGPKG_HAL_H8S_INTC_INIT_DEFINED
    //
    // initialize all interrupts to disabled. We do not need to do this
    // because all interrupts are masked by exr
    //
    .macro  hal_intc_init
    .endm
#endif

    .macro  hal_intc_decode vnum
    .endm
#endif


//=============================================================================
//                               MMU MACROS
// DESCRIPTION:
//     Initialize the MMU, if it is used. On many platforms it is only 
//     possible to control the cacheability of address ranges via the MMU. 
//     Also, it may be necessary to remap RAM and device registers to locations
//     other than their defaults. However, for simplicity, the mapping should 
//     be kept as close to one-to-one physical-to-virtual as possible.
//
// NOTES:
//    The Hitach H8S does not have a MMU
//============================================================================= 
#ifndef CYGPKG_HAL_H8S_MMU_DEFINED
    .macro  hal_mmu_init
    .endm
#endif  


//=============================================================================
//                         MEMORY CONTROLLER MACROS
// DESCRIPTION:
//     Set up the memory controller to access RAM, ROM and I/O devices 
//     correctly. Until this is done it may not be possible to access RAM. 
//     If this is a ROMRAM startup then the program code can now be copied
//     to its RAM address and control transferred to it.
//=============================================================================
#ifndef CYGPKG_HAL_H8S_MEMC_DEFINED
    .macro  hal_memc_init
    .endm
#endif  
    

//=============================================================================
//                                 CACHE MACROS
// DESCRIPTION:
//     Disable and initialize the caches. The caches should not normally be 
//     enabled at this point, but it may be necessary to clear or initialize 
//     them so that they can be enabled later. Some architectures require that 
//     the caches be explicitly reinitialized after a power-on reset.
//
// NOTES:
//     The H8S architecture does not have cache.
//============================================================================= 
#ifndef CYGPKG_HAL_H8S_CACHE_DEFINED
    .macro  hal_cache_init
    .endm
#endif  


//=============================================================================
//                              DIAGNOSTIC MACROS
// DESCRIPTION:
//     Set up diagnostic mechanisms. If the platform includes an LED or LCD 
//     output device, it often makes sense to output progress indications on 
//     this during startup. This helps with diagnosing hardware and
//     software errors.
//============================================================================= 
#ifndef CYGPKG_HAL_H8S_DIAG_DEFINED
    .macro  hal_diag_init
    .endm

    .macro  hal_diag_excpt_start
    .endm

    .macro  hal_diag_intr_start
    .endm

    .macro  hal_diag_restore
    .endm

    .macro  hal_diag_data
    .endm
#endif  


//=============================================================================
//                           TIMER INITIALISATION
// DESCRIPTION:
//     Initialize the timer, clock etc. While the timer used for RTC 
//     interrupts will be initialized later, it may be necessary to set up the 
//     clocks that drive it here.
//============================================================================= 
#ifndef CYGPKG_HAL_H8S_TIMER_DEFINED
    .macro  hal_timer_init
    .endm
#endif  


//=============================================================================
//                           MONITOR INITIALISATION
// DESCRIPTION:
//=============================================================================     
#ifndef CYGPKG_HAL_H8S_MON_DEFINED
    .macro  hal_mon_init
    .endm
#endif


//=============================================================================
//                          LAOD SAVED MACHINE STATE
// DESCRIPTION:
//     Restores a saved machine state from stack. Required for interrupts,
//     exceptions and context swithes.
//============================================================================= 
#ifndef CYGPKG_HAL_H8S_CPU_LOAD_ALL_DEFINED
    .macro hal_cpu_load_all 
    hal_pop_mac                    // pop MAC register if we use it
    ldm     @sp+, er4 - er6        // pop er4-er6 
    ldm     @sp+, er0 - er3        // pop er0-er3
    adds    #4, sp                 // we do not need saved SP  
    .endm
#endif


//=============================================================================
//                     INTERRUPT ENABLE DISABLE MACROS
// DESCRIPTION:
//     Macros for enabling and disabling interrupts. We do this by masking
//     I0-I2 bits in EXR in interrupt control mode 2 or my masking the I bit
//     in CCR in ingterrupt control mode 1.
//============================================================================= 
    //
    // Enable interrupts
    //
    .macro hal_cpu_int_enable
    andc   #0xf8,exr              // clear I0-I2 bits in exr
    .endm       
    
    //
    // Disable interrupts
    //
    .macro hal_cpu_int_disable
    orc    #0x07,exr              // set I0-I2 bits in exr        
    .endm  
    
    //
    // Merge the interrupt enable state of the status register in
    // \sr with the current sr.
    //
    .macro  hal_cpu_int_merge sr wk=r0l
    and.b   #0x07,\sr
    stc     exr,\wk
    and.b   #0xf8,\wk
    or.b    \sr,\wk
    ldc     \wk,exr
    .endm
    
    //
    // Set interrupt level in exr register
    //
    .macro  hal_cpu_set_int_level
    ldc     exr, r0h
    and.b   #0xf8, r0h
    or.b    r0l, r0h
    mov.b   r0h, exr
    .endm

//=-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_ARCH_INC
// end of arch.inc