hal_intr.h

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

#ifndef CYGONCE_HAL_HAL_INTR_H
#define CYGONCE_HAL_HAL_INTR_H
//==========================================================================
//
//      hal_intr.h
//
//      HAL Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    yoshinori sato
// Contributors: yoshinori sato, Uwe Kindler
// Date:         2003-12-06
// Purpose:      Define Interrupt support
// Description:  The macros defined here provide the HAL APIs for handling
//               interrupts and the clock.
// Usage:
//               #include <cyg/hal/hal_intr.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================


//==========================================================================
//                            DOXYGEN FILE HEADER
/// \file    hal_intr.h
/// \brief   Define Interrupt support
/// \author  Yoshinori Sato, Uwe Kindler
/// \date    2003-12-06
///
/// The macros defined here provide the HAL APIs for handling
/// interrupts and the clock.
///
/// Usage:   #include <cyg/hal/hal_intr.h>
//==========================================================================


//==========================================================================
//                                  INCLUDES
//==========================================================================
#include <pkgconf/hal.h>

#if defined(CYGPKG_KERNEL)
#include <pkgconf/kernel.h>
#endif

#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>

#include <cyg/hal/var_intr.h>


//==========================================================================
//                                   H8S VSR
// DESCRIPTION:
//    The H8S architecture supports a number of 128 exception/interrupt 
//    vectors. The vector name are defined within the variant HAL. 
//==========================================================================
#define CYGNUM_HAL_VSR_MIN                     0
#define CYGNUM_HAL_VSR_MAX                     127
#define CYGNUM_HAL_VSR_COUNT                   128


//==========================================================================
//                        H8S INTERRUPT PRIORITY LEVELS
//==========================================================================
#define CYGNUM_HAL_INT_PRIO_0  0x00
#define CYGNUM_HAL_INT_PRIO_1  0x01
#define CYGNUM_HAL_INT_PRIO_2  0x02
#define CYGNUM_HAL_INT_PRIO_3  0x03
#define CYGNUM_HAL_INT_PRIO_4  0x04
#define CYGNUM_HAL_INT_PRIO_5  0x05
#define CYGNUM_HAL_INT_PRIO_6  0x06
#define CYGNUM_HAL_INT_PRIO_7  0x07

#define CYGNUM_HAL_INT_PRIO_LOWEST  CYGNUM_HAL_INT_PRIO_0
#define CYGNUM_HAL_INT_PRIO_HIGHEST CYGNUM_HAL_INT_PRIO_7
//
// When H8S is reseted then the initial values for all priorities
// is CYGNUM_HAL_INT_PRIO_7
//
#define CYGNUM_HAL_INT_PRIO_DEFAULT CYGNUM_HAL_INT_PRIO_7


//==========================================================================
//                          SET VSR TO ECOS HANDLER
// DESCRIPTION:
//     If kernel is present but no kernal api then we have to declare
//     this enum in order to compile the source
//==========================================================================   
#if defined(CYGPKG_KERNEL) && !defined(CYGFUN_KERNEL_API_C) 
enum cyg_ISR_results
{
    CYG_ISR_HANDLED  = 1,       // Interrupt was handled
    CYG_ISR_CALL_DSR = 2        // Schedule DSR
};
#endif


//==========================================================================
//                           STATIC DATA USED BY HAL
//==========================================================================
//
// ISR tables
///
/// Table stores interrupt handlers for each vector (vectors.S)
externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
///
/// Table stores interrupt data to be passed to ISR when executed (vectors.S)
externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
///
/// Table stores interrupt object pointers - required by kernel (vectors.S)
externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
//
// VSR table
///
/// This table contains the vector service routines for all vectors (vectors.S)
///
externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_COUNT];


//==========================================================================
//                               DEFAULT ISR
///
///  Default interrupt service routine in common HAL code
//==========================================================================
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
#define HAL_DEFAULT_ISR hal_default_isr


//==========================================================================
//                      EXECUTE DSR ON INTERRUPT STACK
// DESCRIPTION:
//     A feature that many HALs support is the ability to execute DSRs on 
//     the interrupt stack. This is not an essential feature, and is better 
//     left unimplemented in the initial porting effort. If this is 
//     required, then the macro HAL_INTERRUPT_STACK_CALL_PENDING_DSRS()
//     should be defined to call a function in vectors.S.
//==========================================================================
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
///
/// Execute pending DSRs on the interrupt stack with interrupts enabled.
/// \note This can only be called from code running on a thread stack
///
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
        hal_interrupt_stack_call_pending_DSRs()
//
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
// use them to declare these extern however you want:
//       extern char HAL_INTERRUPT_STACK_BASE[];
//       extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
//
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK


//==========================================================================
//                         INTERRUPT STATE CONTROL
//==========================================================================
///
/// Stores content of interrupt register (EXR)
///
typedef cyg_uint32 CYG_INTERRUPT_STATE;


//==========================================================================
//                         DISABLE INTERRUPTS
// DESCRIPTION:
//     Disables the delivery of interrupts and stores the original state 
//     of the interrupt mask in the variable passed in the old argument.
//
// PARAMETERS:
//     '_old_'  Stores the current interrupt mask before setting the new one
//
// NOTES:
//     If we ware working in interrupt control mode 2 then we have to mask
//     the 3 interrupt mask bits ind EXR register
//==========================================================================
#define HAL_DISABLE_INTERRUPTS(_old_)   \
        asm volatile (                  \
            "sub.l er0,er0\n\t"         \
            "stc exr,r0l\n\t"           \
            "orc #0x7,exr\n\t"          \
            "and.b #0x07,r0l\n\t"       \
            "mov.l er0,%0"              \
            : "=r"(_old_)               \
            :                           \