📄 2.txt
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#include <avr/io.h>
#include <avr/interrupt.h>
enum STATE { S_IDLE, S_PREAMBLE, S_ADDRESS_0, S_ADDRESS_1, S_CODE_0, S_CODE_1, S_LAST };
static uint8_t state = S_IDLE;
#define EVENT_NEW_FRAME 2
uint8_t address = 0;
uint8_t code = 0;
uint8_t packet = 0;
uint8_t ibit = 0;
static uint8_t error = 0;
void necir_init(void)
{
PORTB |= _BV(PINB0); // pullup enable
DDRB &= ~_BV(PINB0); // ICP1 as input
TCNT1 = 0; // start counting from zero
TIMSK |= (1<<TICIE1); // enable input capture interrupts
TCCR1A = 0;
TCCR1B |= (1<<CS11)|(1<<CS10); // timer prescaler 64, ICES1 falling edge
}
uint8_t necir_getaddress(void)
{
return address;
}
uint8_t necir_getcode(void)
{
return code;
}
void necir_superstate(char event)
{
switch (event)
{
case 0:
case 1:
packet < 7)
{
ibit = 0;
++state;
}
error = 0;
break;
case EVENT_NEW_FRAME:
state = S_ADDRESS_0;
ibit = 0;
packet = 0;
error = 0;
break;
default: break;
}
}
void necir_event(char event)
{
switch (state)
{
case S_ADDRESS_0:
necir_superstate(event);
if (state==S_ADDRESS_1)
{
address = packet;
}
break;
case S_CODE_0:
necir_superstate(event);
if (state==S_CODE_1)
{
code = packet;
}
break;
default:
necir_superstate(event);
break;
}
}
#define F_TIMER (F_CPU / 64) // timer prescaler
#define HUNDRED_USEC (F_TIMER / 10000)
ISR(TIMER1_CAPT_vect)
{
unsigned int dpulse = ICR1; // read timer input capture register
TCNT1 = 0; // reset counter
//
// decode the event and dispatch it to the state machine
//
if (dpulse < 12 * HUNDRED_USEC) // 1.2 ms
{
necir_event(0);
}
else if (dpulse < 23 * HUNDRED_USEC) // 2.3 ms
{
necir_event(1);
}
else if (dpulse < 136 * HUNDRED_USEC) // 13.6 ms
{
necir_event(EVENT_NEW_FRAME);
}
}
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