2400verilog.map.rpt

我刚完成的基于Quartus Two 开发环境全部用Verilog硬件描述语言编译无误的MSK调制解调器

Analysis & Synthesis report for 2400verilog
Sun Dec 31 23:53:15 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sun Dec 31 23:53:15 2006        ;
; Quartus II Version          ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name               ; 2400verilog                              ;
; Top-level Entity Name       ; 2400verilog                              ;
; Family                      ; MAX7000S                                 ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option                                                               ; Setting         ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device                                                               ; EPM7128SLC84-10 ;               ;
; Top-level entity name                                                ; 2400verilog     ; 2400verilog   ;
; Family name                                                          ; MAX7000S        ; Stratix       ;
; Use smart compilation                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                  ; Off             ; Off           ;
; Preserve fewer node names                                            ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off             ; Off           ;
; Verilog Version                                                      ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93          ; VHDL93        ;
; State Machine Processing                                             ; Auto            ; Auto          ;
; Extract Verilog State Machines                                       ; On              ; On            ;
; Extract VHDL State Machines                                          ; On              ; On            ;
; Add Pass-Through Logic to Inferred RAMs                              ; On              ; On            ;
; NOT Gate Push-Back                                                   ; On              ; On            ;
; Power-Up Don't Care                                                  ; On              ; On            ;
; Remove Redundant Logic Cells                                         ; Off             ; Off           ;
; Remove Duplicate Registers                                           ; On              ; On            ;
; Ignore CARRY Buffers                                                 ; Off             ; Off           ;
; Ignore CASCADE Buffers                                               ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off             ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto            ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off             ; Off           ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                 ; On              ; On            ;
; Auto Logic Cell Insertion                                            ; On              ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4               ; 4             ;
; Auto Parallel Expanders                                              ; On              ; On            ;
; Auto Open-Drain Pins                                                 ; On              ; On            ;
; Remove Duplicate Logic                                               ; On              ; On            ;
; Auto Resource Sharing                                                ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100             ; 100           ;
; Ignore translate_off and translate_on Synthesis Directives           ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                   ; On              ; On            ;
; HDL message level                                                    ; Level2          ; Level2        ;
+----------------------------------------------------------------------+-----------------+---------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Dec 31 23:53:15 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mzk -c 2400verilog
Info: Found 1 design units, including 1 entities, in source file 2400verilog.v
    Info: Found entity 1: mzk
Error: Entity "mzk" in file 2400verilog.v already exists in file mzk.v File: C:/Documents and Settings/Administrator/桌面/msk_2400/2400verilog/2400verilog.v Line: 1
Info: Found 1 design units, including 1 entities, in source file mzk.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
    Error: Processing ended: Sun Dec 31 23:53:15 2006
    Error: Elapsed time: 00:00:01