2400verilog.v

我刚完成的基于Quartus Two 开发环境全部用Verilog硬件描述语言编译无误的MSK调制解调器

module mzk(clksource,clk,baudsetting,mod_mzk_out,start,demod_mzkin);
		input clksource,start,demod_mzkin;
		input [1:0]baudsetting;
		output clk,mod_mzkout;
		reg   clk,mod_mzkout;
		reg   [10:0]count_num0,count_num1;
		reg   test0,test1;
always @(posedge clksource)
		begin
			if (~start)  begin
							count_num0<=0;
							count_num1<=0;
							//change<=0;
							end
							else
								if(demod_mzkin==1) /*1 is 1200Hz*/
								 
								/*	if (test0==0)
										begin
											count_num1<=0;
											mod_mzkout<=!mod_mzkout;
											 test0<=1;
										end   
										else   */
								 			if (count_num0==255)  
												begin
													mod_mzkout<=!mod_mzkout;
								 					count_num0<=0;
												end
													else count_num0<=count_num0+1;
							 
									else if(demod_mzkin==0)
										  
										/*	if(test1==0)
												begin
													count_num0<=0;
													mod_mzkout<=!mod_mzkout;
													test1<=1;
												end
														esle  */ 
															if (count_num1==512)  
																begin
																	mod_mzkout<=!mod_mzkout;
												 					count_num1<=0;
																end
																	else count_num1<=count_num1+1;
			end
	endmodule