interrupts.c

bf537 CAN接口测试程序

#include "CAN_TX.h"

/*********************************************************************************
**																				**
** CAN_RCV_HANDLER - 	This ISR checks for the highest priority RX Mailbox		**
**						with an active interrupt and clears it.  If the IRQ is	**
**						from MB7, the received data into the DATA3 register is	**
**						displayed on the LEDs.  If desired,	custom processing	**
**						code can be	inserted where indicated.					**
**																				**
*********************************************************************************/
EX_INTERRUPT_HANDLER(CAN_RCV_HANDLER)
{
	char  highMB;				/* Which CAN Registers Should Be Used (1 or 2)	*/
	short mbim_status;			/* Temp Location for Interrupt Status			*/
	short bit_pos = 0;			/* Offset Into MBxIF Registers					*/
	
	mbim_status = *pCAN_MBRIF2;
	
	if (mbim_status == 0)				/* If High 16 MBs Have No Active IRQ	*/
	{
		mbim_status = *pCAN_MBRIF1;		/* Check Low 16 MBs						*/
		highMB = 0;						/* Clear High/Low* Indicator			*/
	}
	
	else								/* Otherwise, High MB IRQ Found			*/
		highMB = 1;						/* Set High/Low* Indicator				*/

	while (!(mbim_status & 0x8000))		/* Scan Status For Highest MB IRQ		*/
	{
		mbim_status <<= 1;
		bit_pos++;						/* bit_pos Contains Offset from MB31	*/
	}

	bit_pos = 1 << (15 - bit_pos);		/* Place Mask for Clearing Status 		*/

	if (highMB)							/* High Indicator Means MBRIF2 Register	*/
	{
		/* /// Insert Processing Code Here ///									*/
		*pCAN_MBRIF2 	= bit_pos;	/* W1C MB RX IRQ							*/
		*pCAN_RMP2 		= bit_pos;	/* W1C Status Bit							*/
	}
	
	else
	{
		/* /// Insert Processing Code Here ///									*/
		if (bit_pos == MBRIF7)						/* If Active IRQ is MB7		*/
			/********************************************************************
			 * RX Data Is in Bits 15:8 of CAN_MB7_DATA3							*
			 * LEDs Are Mapped to Bits 11:6 of PORTFIO							*
			 * To Align: CAN_MB7_DATA3 >> 2										*
			 ********************************************************************/
			*pPORTFIO = (*(pCAN_MB_DATA3(7)) >> 2);
			
		*pCAN_MBRIF1 	= bit_pos;	/* W1C MB RX IRQ							*/
		*pCAN_RMP1 		= bit_pos;	/* W1C Status Bit							*/
	}
	
	ssync();	
} /* end CAN_RCV_HANDLER														*/


/*********************************************************************************
**																				**
** CAN_XMT_HANDLER - 	This ISR checks for the highest priority TX Mailbox		**
**						with an active interrupt and clears it.  If desired,	**
**						custom processing code can be inserted where indicated.	**
**																				**
*********************************************************************************/
EX_INTERRUPT_HANDLER(CAN_XMT_HANDLER)
{
	char  highMB;				/* Which CAN Registers Should Be Used (1 or 2)	*/
	short mbim_status;			/* Temp Location for Interrupt Status			*/
	short bit_pos = 0;			/* Offset Into MBxIF Registers					*/
	
	mbim_status = *pCAN_MBTIF2;			/* Check High MBoxes First				*/
	
	if (mbim_status == 0)				/* If No High MB Interrupts				*/
	{
		mbim_status = *pCAN_MBTIF1;		/* Check Low MB Interrupts				*/
		highMB = 0;						/* Clear High/Low* Mailbox Indicator	*/
	}
	
	else								/* Otherwise, it is a High Mailbox		*/
		highMB = 1;						/* Set High/Low* Mailbox Indicator		*/

	while (!(mbim_status & 0x8000))		/* Find Highest Mailbox W/ Active IRQ	*/
	{
		mbim_status <<= 1;
		bit_pos++;						/* bit_pos Contains Offset from MB31	*/
	} /* Interrupting Mailbox Found												*/
	
	bit_pos = 1 << (15 - bit_pos);		/* Place Mask for Clearing Status 		*/

	if (highMB)		/* Process High Mailbox IRQ									*/
	{
		/* /// Insert Processing Code Here ///									*/
		*pCAN_MBTIF2 	= bit_pos;			/* W1C Detected IRQ					*/
		*pCAN_TA2		= bit_pos;			/* W1C Status Bit					*/
	}
	
	else			/* Else, Process Low Mailbox IRQ							*/
	{
		/* /// Insert Processing Code Here ///									*/
		*pCAN_MBTIF1 	= bit_pos;			/* W1C Detected IRQ					*/
		*pCAN_TA1		= bit_pos;			/* W1C Status Bit					*/
	}
	
	ssync();
} /* end CAN_XMT_HANDLER														*/


/*********************************************************************************
**																				**
** PFA_HANDLER -	This ISR checks for which push-button generated the IRQ,	**
**					sets up the CAN DATA3 register with the correct command,	**
**					clears the PFx IRQ, and requests a CAN transmit for MB24.	**
**																				**
*********************************************************************************/
EX_INTERRUPT_HANDLER(PFA_HANDLER)
{
	/* Single Byte CAN Data Is Placed In Upper Byte of DATA3					*/
	switch(*pPORTFIO & (PF5|PF4|PF3|PF2))	/* Check for Button Push			*/
	{
		case (0x04):	/* PB1 = CAN Blink										*/
						*(pCAN_MB_DATA3(24)) = 0x0100;	/* 1 = Blink			*/
						*pPORTFIO_CLEAR = PF2;		/* Clear IRQ				*/
						break;

		case (0x08):	/* PB2 = CAN Scroll Right								*/
						*(pCAN_MB_DATA3(24)) = 0x0200;	/* 2 = Scroll Right		*/
						*pPORTFIO_CLEAR = PF3;		/* Clear IRQ				*/
						break;

		case (0x10):	/* PB3 = CAN Scroll Left								*/
						*(pCAN_MB_DATA3(24)) = 0x0300;	/* 3 = Scroll Left		*/
						*pPORTFIO_CLEAR = PF4;		/* Clear IRQ				*/
						break;

		case (0x20):	/* PB4 = Turn LEDs Off									*/
						*(pCAN_MB_DATA3(24)) = 0x0400;	/* 4 = Shut Off LEDs	*/
						*pPORTFIO_CLEAR = PF5;		/* Clear IRQ				*/
						break;
						
		default: 		/* Multiple Buttons Pressed								*/
						*(pCAN_MB_DATA3(24)) = 0x0400;	/* 4 = Shut Off LEDs	*/
						/* Clear All IRQs										*/
						*pPORTFIO_CLEAR = *pPORTFIO & (PF5|PF4|PF3|PF2);
	}
	
	ssync();

	*pCAN_TRS2 = CAN_TX_MB_HI;	/* Send New Command Data Over CAN				*/
	ssync();
} /* end PFA_HANDLER															*/