📄 f020com.lst
字号:
00B9 +1 178 PT0 BIT IP.1 ; TIMER 0 PRIORITY
00BA +1 179 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
00BB +1 180 PT1 BIT IP.3 ; TIMER 1 PRIORITY
00BC +1 181 PS BIT IP.4 ; SERIAL PORT PRIORITY
00BD +1 182 PT2 BIT IP.5 ; TIMER 2 PRIORITY
+1 183 ;
+1 184 ; SMB0CN C0H
00C0 +1 185 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
00C1 +1 186 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
00C2 +1 187 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C3 +1 188 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
00C4 +1 189 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
00C5 +1 190 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG
A51 MACRO ASSEMBLER F020COM 01/13/2008 10:31:39 PAGE 4
00C6 +1 191 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE
+1 192 ;
+1 193 ; T2CON C8H
00C8 +1 194 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
00C9 +1 195 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
00CA +1 196 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
00CB +1 197 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
00CC +1 198 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
00CD +1 199 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
00CE +1 200 EXF2 BIT T2CON.6 ; EXTERNAL FLAG
00CF +1 201 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG
+1 202 ;
+1 203 ; PSW D0H
00D0 +1 204 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
00D1 +1 205 F1 BIT PSW.1 ; USER FLAG 1
00D2 +1 206 OV BIT PSW.2 ; OVERFLOW FLAG
00D3 +1 207 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
00D4 +1 208 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
00D5 +1 209 F0 BIT PSW.5 ; USER FLAG 0
00D6 +1 210 AC BIT PSW.6 ; AUXILIARY CARRY FLAG
00D7 +1 211 CY BIT PSW.7 ; CARRY FLAG
+1 212 ;
+1 213 ; PCA0CN D8H
00D8 +1 214 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
00D9 +1 215 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
00DA +1 216 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
00DB +1 217 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
00DC +1 218 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
00DE +1 219 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
00DF +1 220 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+1 221 ;
+1 222 ; ADC0CN E8H
00E8 +1 223 AD0LJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
00E9 +1 224 AD0WINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
00EA +1 225 AD0STM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
00EB +1 226 AD0STM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
00EC +1 227 AD0BUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG
00ED +1 228 AD0INT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG
00EE +1 229 AD0TM BIT ADC0CN.6 ; ADC 0 TRACK MODE
00EF +1 230 AD0EN BIT ADC0CN.7 ; ADC 0 ENABLE
+1 231 ;
+1 232 ; SPI0CN F8H
00F8 +1 233 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
00F9 +1 234 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE
00FA +1 235 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT
00FB +1 236 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG
00FC +1 237 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
00FD +1 238 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
00FE +1 239 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
00FF +1 240 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
241
242
0000 243 ORG 0000H
0000 020100 244 LJMP MAIN
0023 245 ORG 0023H
0023 02015B 246 LJMP SEND
0100 247 ORG 0100H
0100 900167 248 MAIN: MOV DPTR,#TABLE
0103 7D0F 249 MOV R5,#0FH
0105 120150 250 LCALL WDT
0108 120111 251 LCALL PORT_INIT
010B 120124 252 LCALL Oscillator_Init
010E 120138 253 LCALL UART_Init
254
255
256 ;----------------------------------------------------------
A51 MACRO ASSEMBLER F020COM 01/13/2008 10:31:39 PAGE 5
0111 257 PORT_INIT:
0111 75A6FF 258 MOV P2MDOUT,#0FFH ;设置P2，P3口为推挽方式
0114 75A7FF 259 MOV P3MDOUT,#0FFH
0117 75E104 260 MOV XBR0,#04H
011A 75E288 261 MOV XBR1,#88H
011D 75E341 262 MOV XBR2,#41H
0120 75A337 263 MOV EMI0CF,#37H ;use the internal XRAM only
0123 22 264 RET
265 ;----------------------------------------------------------
0124 266 Oscillator_Init:
0124 75B167 267 MOV OSCXCN,#067h
0127 781E 268 MOV R0,#030 ; Wait 1ms for initialization
0129 269 Osc_Wait1:
0129 E4 270 CLR A
012A D5E0FD 271 DJNZ ACC,$
012D D8FA 272 DJNZ R0,Osc_Wait1
012F 273 Osc_Wait2:
012F E5B1 274 MOV A,OSCXCN
0131 30E7FB 275 JNB ACC.7,Osc_Wait2
0134 75B20C 276 MOV OSCICN,#00Ch
0137 22 277 RET
278
279 ;---------------------------------------------------------
280
0138 281 UART_Init:
0138 7598DA 282 MOV SCON0,#0DAH
013B 758840 283 MOV TCON,#40H
013E 758920 284 MOV TMOD,#20H
0141 758BFD 285 MOV TL1,#0FDH ;BAUD rate is 9600bps
0144 758DFD 286 MOV TH1,#0FDH
0147 D2AF 287 SETB EA
0149 D2AC 288 SETB ES
014B D28E 289 SETB TR1
014D 80FE 290 SJMP $
014F 22 291 RET
292 ;---------------------------------------------------------
0150 C2AF 293 WDT: CLR EA ;Forbid the WDT
0152 75FFDE 294 MOV WDTCN,#0DEH
0155 75FFAD 295 MOV WDTCN,#0ADH
0158 D2AF 296 SETB EA
015A 22 297 RET
298 ;---------------------------------------------------------
299 ;*********************************************************
300
015B 301 SEND:
015B E4 302 CLR A
015C 93 303 MOVC A,@A+DPTR
304 ;MOV A,#03H
015D F599 305 MOV SBUF0,A
306 ;jnb ti,$
015F C299 307 CLR TI
0161 A3 308 INC DPTR
0162 DD02 309 DJNZ R5,LOOP
0164 C2AF 310 CLR EA
0166 32 311 LOOP: RETI
312 ;---------------------------------------------------------
313
314
0167 01020304 315 TABLE: DB 01H,02H,03H,04H,05H,06H,07H,08H,09H
016B 05060708
016F 09
0170 0A0B0C0D 316 DB 0AH,0BH,0CH,0DH,0EH,0FH
0174 0E0F
317 END
A51 MACRO ASSEMBLER F020COM 01/13/2008 10:31:39 PAGE 6
A51 MACRO ASSEMBLER F020COM 01/13/2008 10:31:39 PAGE 7
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
AA . . . . . . . . B ADDR 00C0H.2 A
AC . . . . . . . . B ADDR 00D0H.6 A
ACC. . . . . . . . D ADDR 00E0H A
AD0BUSY. . . . . . B ADDR 00E8H.4 A
AD0EN. . . . . . . B ADDR 00E8H.7 A
AD0INT . . . . . . B ADDR 00E8H.5 A
AD0LJST. . . . . . B ADDR 00E8H.0 A
AD0STM0. . . . . . B ADDR 00E8H.2 A
AD0STM1. . . . . . B ADDR 00E8H.3 A
AD0TM. . . . . . . B ADDR 00E8H.6 A
AD0WINT. . . . . . B ADDR 00E8H.1 A
ADC0CF . . . . . . D ADDR 00BCH A
ADC0CN . . . . . . D ADDR 00E8H A
ADC0GTH. . . . . . D ADDR 00C5H A
ADC0GTL. . . . . . D ADDR 00C4H A
ADC0H. . . . . . . D ADDR 00BFH A
ADC0L. . . . . . . D ADDR 00BEH A
ADC0LTH. . . . . . D ADDR 00C7H A
ADC0LTL. . . . . . D ADDR 00C6H A
ADC1 . . . . . . . D ADDR 009CH A
ADC1CF . . . . . . D ADDR 00ABH A
ADC1CN . . . . . . D ADDR 00AAH A
AMX0CF . . . . . . D ADDR 00BAH A
AMX0SL . . . . . . D ADDR 00BBH A
AMX1SL . . . . . . D ADDR 00ACH A
B. . . . . . . . . D ADDR 00F0H A
CCF0 . . . . . . . B ADDR 00D8H.0 A
CCF1 . . . . . . . B ADDR 00D8H.1 A
CCF2 . . . . . . . B ADDR 00D8H.2 A
CCF3 . . . . . . . B ADDR 00D8H.3 A
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