📄 start_v2.lst
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158 ;
159 ; <q> ZSC: Enable Zero Cycle Jump Cache (CPUCON2.5)
0001 160 _ZSC EQU 1 ; 0 = Zero Cycle Jump Cache disabled
161 ; 1 = Zero Cycle Jump Cache enabled
162 ;
163 ; <q> STEN: Enable Stall Instruction (CPUCON2.6)
0000 164 _STEN EQU 0 ; 0 = Stall instruction disabled /Dave/
165 ; 1 = Stall instruction enabled
166 ;
167 ; <q> EIOIAEN: Early IO Injection Acknowledge guaranteed (CPUCON2.7)
0001 168 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
169 ; ; 1 = Injection ack. by destructive read guaranteed
170 ;
171 ; <q> BYPF: Enable Fetch Bypass Control (CPUCON2.8)
0001 172 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled /Dave/
173 ; 1 = Bypass Path from Fetch to Decode enabled
174 ;
175 ; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
0001 176 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled /Dave/
177 ; 1 = Bypass Path from Prefetch to Decode enabled
178 ;
179 ; <o> FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
180 ; <0=> FIFO disabled <1=> 1 instruction
181 ; <2=> 2 instructions <3=> 3 instructions
0003 182 _FIFOFED EQU 3 ; 0 = FIFO disabled /Dave/
183 ; 1 = FIFO filled with up to 1 instruction per cycle
184 ; 2 = FIFO filled with up to 2 instructions per cycle
185 ; 3 = FIFO filled with up to 3 instructions per cycle
186 ;
187 ;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
0008 188 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO) /Dave/
189 ; 1 = 1 FIFO entry
190 ; ...
A166 MACRO ASSEMBLER START_V2 09/04/2007 16:24:43 PAGE 4
191 ; 8 = 8 FIFO entries
192 ; 9 - 15 = reserved
193 ;</e>
194
195 ; <e> Definitions for Internal Memory Block Control Register IMBCTR
196 ; =================================================================
197 ;
198 ; INIT_IMBCTR: Init IMBCTR register
199 ; --- <i>Set INIT_IMBCTR to initilize the IMBCTR register
200 $SET (INIT_IMBCTR = 0) ; default: do not initilize IMBCTR
201 ;
202 ; <o> WSFLASH: Wait States for the Flash Memory (IMBCTR.0 .. IMBCTR.1)
203 ; <0=> No waitstates (Flash Read in one clock)
204 ; <1=> One waitstate (Flash Read in two clocks)
205 ; <2=> Two waitstates (Flash Read in three clocks)
206 ; <3=> Three waitstates (Flash Read in four clocks)
0001 207 _WSFLASH EQU 1 ; 0 = No waitstates
208 ; 1 = One waitstate
209 ; 2 = Two waitstates
210 ; 3 = Three waitstates
211 ;
212 ; <q> WSRAM: Wait State for Program RAM Access (IMBCTR.2)
213 ; <i> when enabled, Program SRAM has same timing behaviour as Flash memory
0000 214 _WSRAM EQU 0 ; 0 = Program SRAM accessed with max. speed
215 ; 1 = Program SRAM access like Flash Memory
216 ;
217 ;</e>
218
219 ;</h>
220 ; <e> OCDS Debug Peripheral Suspend Configuration
221 ; ===============================================
222 ; <i> Initialize OPSEN to stop specific peripherals during debugging
0000 223 _OCDS_PSTOP EQU 0 ; 0 = OPSEN is not modified by startup code
224 ; 1 = OPSEN is modified with the value below
225 ; <i> Selects the peripherals that are halted by OCDS debugging
226 ; <i> when a breakpoint is reached
227 ; <q.0> Stop Analog/Digital Converter
228 ; <q.1> Stop UART ASC0
229 ; <q.2> Stop Synchronus Serial Cnl0 SSC0
230 ; <q.3> Stop Timer Block GPT
231 ; bit 4 reserved
232 ; <q.5> Stop on-chip Flash Memory Module
233 ; <q.6> Stop CAPCOM Unit 1
234 ; <q.7> Stop CAPCOM Unit 2
235 ; <q.8> Stop CAPCOM Unit 6
236 ; bit 9 reserved
237 ; <q.10> Stop UART ASC1
238 ; <q.11> Stop I2C Bus Module
239 ; <q.12> Stop SDLM (J1850) Module
240 ; <q.13> Stop on-chip CAN Module
241 ; <q.14> Stop Real Time Clock
242 ; <q.15> Stop Synchronus Serial Cnl1 SSC1
243
244 ; value for OPSEN (OCE/OCDS Peripheral Suspend Register)
0000 245 _OPSEN EQU 0
246 ;</e>
247
248 ; <h> Peripheral Configuration
249 ; ============================
250 ;
251 ; <e> Definitions for System Configuration Register SYSCON1
252 ; =========================================================
253 ;
254 ; INIT_SYSCON1: Init SYSCON1 register
255 ; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
256 $SET (INIT_SYSCON1 = 0) ; /Dave/
A166 MACRO ASSEMBLER START_V2 09/04/2007 16:24:43 PAGE 5
257 ;
258 ; <q> SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
259 ; <0=> IDLE mode upon IDLE instr. <1=> SLEEP mode upon IDLE instr.
0000 260 _SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction /Dave/
261 ; 1 = SLEEP mode entered upon IDLE instruction
262 ; 2 - 3 = reserved
263 ;
264 ; <q> PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
265 ; <0=>Port drivers are always ON <1=>Port drivers are off in IDLE/Sleep mode
266 ; <2=>Port drivers are off in Powerdown mode
0000 267 _PDCFG EQU 0 ; 0 = Port drivers are always ON (default) /Dave/
268 ; 1 = Port drivers are off in IDLE or Sleep mode
269 ; 2 = Port drivers are off in Powerdown mode
270 ; 3 = reserved
271 ;
272 ; <o> PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
273 ; <0=> Program Flash always ON <1=>Program Flash OFF in IDLE/Sleep mode
0000 274 _PFCFG EQU 0 ; 0 = Program Flash is always ON (default) /Dave/
275 ; 1 = Program Flash is off in IDLE or Sleep mode
276 ; 2 - 3 = reserved
277 ;
278 ; <o> CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
279 ; <0=>CPU clock = PLL frequency <1=>CPU clock = PLL frequency / 2
0000 280 _CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency /Dave/
281 ; 1 = clock signal for CPU is PLL frequency / 2
282 ; 2 - 7 = reserved
283 ; </e>
284 ;
285 ; <e> Definitions for System Configuration Register SYSCON3
286 ; =========================================================
287 ;
288 ; INIT_SYSCON3: Init SYSCON3 register
289 ; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
290 $SET (INIT_SYSCON3 = 1) ; /Dave/
291 ;
292 ; SYSCON3: Power Management (disable on-chip peripherals)
293 ;
294 ;<q> Disable Analog/Digital Converter
0000 295 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
296 ;<q> Disable UART ASC0
0000 297 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1) /Dave/
298 ;<q> Disable Synchronus Serial Cnl0 SSC0
0000 299 SSC0DIS EQU 0 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2) /Dave/
300 ;<q> Disable Timer Block GPT
0000 301 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3) /Dave/
302 ; reserved (SYSCON3.4)
303 ;<q> Disable on-chip Flash Memory Module
0000 304 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5) /Dave/
305 ;<q> Disable CAPCOM Unit 1
0001 306 CC1DIS EQU 1 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6) /Dave/
307 ;<q> Disable CAPCOM Unit 2
0001 308 CC2DIS EQU 1 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7) /Dave/
309 ;<q> Disable CAPCOM Unit 6
0001 310 CC6DIS EQU 1 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8) /Dave/
311 ; reserved (SYSCON3.9)
312 ;<q> Disable UART ASC1
0001 313 ASC1DIS EQU 1 ; 1 = disable UART ASC1 (SYSCON3.10) /Dave/
314 ;<q> Disable I2C Bus Module
0001 315 I2CDIS EQU 1 ; 1 = disable I2C Bus Module (SYSCON3.11) /Dave/
316 ;<q> Disable SDLM (J1850) Module
0000 317 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12) /Dave/
318 ;<q> Disable on-chip CAN Module
0000 319 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13) /Dave/
320 ;<q> Disable Real Time Clock
0000 321 RTCDIS EQU 0 ; 1 = disable Real Time Clock (SYSCON3.14)
322 ;<q> Disable Synchronus Serial Cnl1 SSC1
A166 MACRO ASSEMBLER START_V2 09/04/2007 16:24:43 PAGE 6
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