📄 start_v2.a66
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; <o>PHC4: Phase C clock cycle (TCONCS4.3 .. TCONCS4.4) <0-3>
_PHC4 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHD4: Phase D clock cycle (TCONCS4.5) <0-1>
_PHD4 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; <o> PHE4: Phase E clock cycle (TCONCS4.6 .. TCONCS4.10) <1-32> <#-1>
_PHE4 EQU 8 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF4: Phase F read clock cycle (TCONCS4.11 .. TCONCS4.12) <0-3>
_RDPHF4 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF4: Phase F write clock cycle (TCONCS4.13 .. TCONCS4.14) <0-3>
_WRPHF4 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS5 Area
; =============================================
;
; --- Set CONFIG_CS5 = 1 to initialize the ADDRSEL5/FCONCS5/TCONCS5 registers
$SET (CONFIG_CS5 = 0)
;
; <h>Definitions for Address Select register ADDRSEL5
; ===================================================
; <o> CS5 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR5 EQU 0x500000 ; Set CS5# Start Address (default 100000H)
; <o> CS5 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE5 EQU 1024*KB ; Set CS5# Size (default 1024*KB = 1*MB)
; possible values for _SIZE5 are:
; 4*KB (gives RGSZ5 = 0)
; 8*KB (gives RGSZ5 = 1)
; 16*KB (gives RGSZ5 = 2)
; 32*KB (gives RGSZ5 = 3)
; 64*KB (gives RGSZ5 = 4)
; 128*KB (gives RGSZ5 = 5)
; 256*KB (gives RGSZ5 = 6)
; 512*KB (gives RGSZ5 = 7)
; 1024*KB or 1*MB (gives RGSZ5 = 8)
; 2048*KB or 2*MB (gives RGSZ5 = 9)
; 4096*KB or 4*MB (gives RGSZ5 = 10)
; 8192*KB or 8*MB (gives RGSZ5 = 11)
; (RGSZ5 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS5
; =======================================================
;
; <q> ENCS5: Enable Chip Select (FCONCS5.0)
_ENCS5 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; <q> RDYEN5: Ready Enable (FCONCS5.1)
_RDYEN5 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1
; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
;
; <o> RDYMOD2: Ready Mode (FCONCS5.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD5 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; <o> BTYP2: Bus Type Selection (FCONCS5.4 .. FCONCS5.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP5 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS5: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA5: Phase A clock cycle (TCONCS5.0 .. TCONCS5.1) <0-3>
_PHA5 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHB5: Phase B clock cycle (TCONCS5.2) <1-2> <#-1>
_PHB5 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; <o>PHC5: Phase C clock cycle (TCONCS5.3 .. TCONCS5.4) <0-3>
_PHC5 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHD5: Phase D clock cycle (TCONCS5.5) <0-1>
_PHD5 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; <o> PHE5: Phase E clock cycle (TCONCS5.6 .. TCONCS5.10) <1-32> <#-1>
_PHE5 EQU 8 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF5: Phase F read clock cycle (TCONCS5.11 .. TCONCS5.12) <0-3>
_RDPHF5 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF5: Phase F write clock cycle (TCONCS5.13 .. TCONCS5.14) <0-3>
_WRPHF5 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS6 Area
; =============================================
;
; --- Set CONFIG_CS6 = 1 to initialize the ADDRSEL6/FCONCS6/TCONCS6 registers
$SET (CONFIG_CS6 = 0)
;
; <h>Definitions for Address Select register ADDRSEL6
; ===================================================
; <o> CS6 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR6 EQU 0x600000 ; Set CS2# Start Address (default 100000H)
; <o> CS6 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE6 EQU 1024*KB ; Set CS6# Size (default 1024*KB = 1*MB)
; possible values for _SIZE6 are:
; 4*KB (gives RGSZ6 = 0)
; 8*KB (gives RGSZ6 = 1)
; 16*KB (gives RGSZ6 = 2)
; 32*KB (gives RGSZ6 = 3)
; 64*KB (gives RGSZ6 = 4)
; 128*KB (gives RGSZ6 = 5)
; 256*KB (gives RGSZ6 = 6)
; 512*KB (gives RGSZ6 = 7)
; 1024*KB or 1*MB (gives RGSZ6 = 8)
; 2048*KB or 2*MB (gives RGSZ6 = 9)
; 4096*KB or 4*MB (gives RGSZ6 = 10)
; 8192*KB or 8*MB (gives RGSZ6 = 11)
; (RGSZ6 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS6
; =======================================================
;
; <q> ENCS6: Enable Chip Select (FCONCS6.0)
_ENCS6 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; <q> RDYEN6: Ready Enable (FCONCS6.1)
_RDYEN6 EQU 0 ; 0 = Access time controlled by TCONCS6.PHE1
; 1 = Access time cont. by TCONCS6.PHE1 and READY signal
;
; <o> RDYMOD6: Ready Mode (FCONCS6.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD6 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; <o> BTYP6: Bus Type Selection (FCONCS6.4 .. FCONCS6.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP6 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS6: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA6: Phase A clock cycle (TCONCS6.0 .. TCONCS6.1) <0-3>
_PHA6 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHB6: Phase B clock cycle (TCONCS6.2) <1-2> <#-1>
_PHB6 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; <o>PHC6: Phase C clock cycle (TCONCS6.3 .. TCONCS6.4) <0-3>
_PHC6 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHD6: Phase D clock cycle (TCONCS6.5) <0-1>
_PHD6 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; <o> PHE6: Phase E clock cycle (TCONCS6.6 .. TCONCS6.10) <1-32> <#-1>
_PHE6 EQU 8 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF6: Phase F read clock cycle (TCONCS6.11 .. TCONCS6.12) <0-3>
_RDPHF6 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF6: Phase F write clock cycle (TCONCS6.13 .. TCONCS6.14) <0-3>
_WRPHF6 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS7 Area
; =============================================
;
; --- Set CONFIG_CS7 = 1 to initialize the ADDRSEL7/FCONCS7/TCONCS7 registers
$SET (CONFIG_CS7 = 0)
;
; <h>Definitions for Address Select register ADDRSEL7
; ===================================================
; <o> CS7 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR7 EQU 0x700000 ; Set CS7# Start Address (default 100000H)
; <o> CS7 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE7 EQU 1024*KB ; Set CS7# Size (default 1024*KB = 1*MB)
; possible values for _SIZE7 are:
; 4*KB (gives RGSZ7 = 0)
; 8*KB (gives RGSZ7 = 1)
; 16*KB (gives RGSZ7 = 2)
; 32*KB (gives RGSZ7 = 3)
; 64*KB (gives RGSZ7 = 4)
; 128*KB (gives RGSZ7 = 5)
; 256*KB (gives RGSZ7 = 6)
; 512*KB (gives RGSZ7 = 7)
; 1024*KB or 1*MB (gives RGSZ7 = 8)
; 2048*KB or 2*MB (gives RGSZ7 = 9)
; 4096*KB or 4*MB (gives RGSZ7 = 10)
; 8192*KB or 8*MB (gives RGSZ7 = 11)
; (RGSZ7 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS7
; =======================================================
;
; <q> ENCS7: Enable Chip Select (FCONCS7.0)
_ENCS7 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; <q> RDYEN7: Ready Enable (FCONCS7.1)
_RDYEN7 EQU 0 ; 0 = Access time controlled by TCONCS7.PHE1
; 1 = Access time cont. by TCONCS7.PHE1 and READY signal
;
; <o> RDYMOD7: Ready Mode (FCONCS7.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD7 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; <o> BTYP7: Bus Type Selection (FCONCS7.4 .. FCONCS7.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP7 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS7: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA7: Phase A clock cycle (TCONCS7.0 .. TCONCS7.1) <0-3>
_PHA7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHB7: Phase B clock cycle (TCONCS7.2) <1-2> <#-1>
_PHB7 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; <o>PHC7: Phase C clock cycle (TCONCS7.3 .. TCONCS7.4) <0-3>
_PHC7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>PHD27 Phase D clock cycle (TCONCS2.5) <0-1>
_PHD7 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; <o> PHE7: Phase E clock cycle (TCONCS7.6 .. TCONCS7.10) <1-32> <#-1>
_PHE7 EQU 8 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF7: Phase F read clock cycle (TCONCS7.11 .. TCONCS7.12) <0-3>
_RDPHF7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF7: Phase F write clock cycle (TCONCS7.13 .. TCONCS7.14) <0-3>
_WRPHF7 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;</h> </e>
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