start_v2.a66

xc164 IAP （flash in chip)例子

;
; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
_RODIS    EQU    0      ; 0 = RSTOUT is controlled by other mechanism
                        ; 1 = RSTOUT is deactivated
;
;</e>
;
;
; <e> Definitions for PLL Control Register PLLCON
; ===========================================
;
; INIT_PLLCON: Init PLLCON register
; --- Set INIT_PLLCON = 0 to initilize the PLLCON register
$SET (INIT_PLLCON = 1)
;
; <o> PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3) <0-14>
_PLLODIV  EQU    9      ; 0 .. 14  Fpll = Fvco / (PLLODIV+1)
                        ; 15 = reserved
;
; <o> PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5) <0-3>
; <i> Fin = Fosc / (PLLIDIV+1)
_PLLIDIV  EQU    0      ; 0 .. 3   Fin = Fosc / (PLLIDIV+1)
;
; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
_PLLVB    EQU   2      ; ValueVCO output frequency    Base frequency
                        ; 0 = 100...150 MHz            20...80 MHz
                        ; 1 = 150...200 MHz            40...130 MHz
                        ; 2 = 200...250 MHz [def.]     60...180 MHz
                        ; 3 = (250...300 MHz) Reserved
;
; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <6-31>
; <i> Fvco = Fin * (PLLMUL+1)
_PLLMUL   EQU    24     ; 7 .. 31  Fvco = Fin * (PLLMUL+1)
                        ; 0 .. 6 = reserved
;
; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
; <0=> Bypass PLL clock mult., the VCO is off   <1=> Bypass PLL clock mult., the VCO is running
; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock connected
_PLLCTRL  EQU    3      ; 0 = Bypass PLL clock mult., the VCO is off
                        ; 1 = Bypass PLL clock mult., the VCO is running
                        ; 2 = VCO clock used, input clock switched off
                        ; 3 = VCO clock used, input clock connected
;
; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
; <0=> Register PLLCON may be written  <1=> Write cycles to register PLLCON are ignored
_PLLWRI   EQU    0      ; 0 = Register PLLCON may be written
                        ; 1 = Write cycles to register PLLCON are ignored
;</e>
;
; <e> Definitions for Watchdog Timer Control Register WDTCON
; ======================================================
;
; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initilize the WDTCON register
$SET (WATCHDOG = 0)     ; 0 = Disabled Hardware watchdog
;
; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
; <0=> Peripheral Frequency divided by 2  <1=> Peripheral Frequency divided by 128 
; <2=> Peripheral Frequency divided by 4  <3=> Peripheral Frequency divided by 256
_WDTIN    EQU    1      ; 0 = frequency f_peripheral / 2   (CPU default)  
                        ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
                        ; 2 = frequency f_peripheral / 4
                        ; 3 = frequency f_peripheral / 256
;
; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
_WDTREL   EQU    0      
;
;</e>
; <e> Definitions for Frequency Output Signal FOCON
; =================================================
;
; INIT_FOCON: Init FOCON register
; --- Set INIT_FOCON = 0 to initilize the FOCON register
$SET (INIT_FOCON = 1)
;
; <o> CLKEN: CLKOUT Enable (FOCON.7)
; <0=> P3.15 is IO <1=> P3.15 is CLKOUT
_CLKEN    EQU     0     ; 0 = P3.15 is IO pin when _FOUT is 0
                        ; 1 = P3.15 outputs signal CLKOUT
;
; <o> FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13) <0-63>
; <i> Is copied to FOCNT upon each underflow of FOCNT
_FORV     EQU     0
;
; <o> FOSS: Frequency Output Signal Select (FOCON.14)
; <0=> Output of Toggle Latch  <1=> Output of Reload Counter
_FOSS     EQU     0     ; 0 = Output of the toggle latch; 0.5 duty cycle
                        ; 1 = Output of reload counter; duty cycle depends on FORV
;
; <o> FOEN: Frequency Output Enable (FOCON.15)
; <0=> P3.15 is IO <1=> P3.15 outputs f_OUT
_FOEN     EQU     0     ; 0 = P3.15 is IO pin when _CLKEN is 0
                        ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
;</e>
;
;<h> External Bus Configuration
;
; <e> Configure External Bus (EBC) Behaviour
; ==========================================
;
; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
$SET (CONFIG_EBC = 0)   ; 0 = EBCMOD0/EBCMOD1 are set during reset according the 
                        ;     of configuration bus (typical Port0) values.
                        ; 1 = the following external bus configuration values
                        ;      are written to EBCMOD and BUSACT0
;
; <h>Definitions for EBC Mode 0 register EBCMOD0
; ===========================================
;
; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
; <i> Number of active Address Lines (A16-A23)
_SAPEN      EQU    0    ; 0 = No segment address pins enabled
                        ; 1 = One (A16) segment address pin enabled
                        ; : = :        
                        ; 8 = Eight (A16 .. A23) address pins enabled
                        ; 9 - 15 = reserved
;
; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
; <i> Number of active ChipSelect pins
_CSPEN      EQU    8    ; 0 = No CS pins enabled
                        ; 1 = One CS (CS0) pin enabled
                        ; : = :
                        ; 8 = Eight CS (CS0 .. CS7) pins enabled
                        ; 9 - 15 = reserved
; Note: the number of available CS pins depends on the chip used
;
; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
_ARBEN      EQU    0    ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
                        ; 1 = HOLD, HLDA and BREQ pins act normally
;
; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
; <0=> Master Mode  <1=> Slave Mode
_SLAVE      EQU    0    ; 0 = Bus arbiter acts in master mode
                        ; 1 = Bus arbiter acts in slave mode
;
; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
_EBCDIS     EQU    0    ; 0 = EBC is using the pins for external bus
                        ; 1 = EBC off (pins to be used as GPIO if implemented)
;
; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
; <0=> WR and BHE  <1=> WRL and WRH
_WRCFG      EQU    0    ; 0 = Pins act as WR and BHE
                        ; 1 = Pins act as WRL and WRH
;
; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
_BYTDIS     EQU    0    ; 0 = BHE enabled
                        ; 1 = BHE disabled (GPIO function if implemented)
;
; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
_ALEDIS     EQU    0    ; 0 = ALE pin enabled
                        ; 1 = ALE pin disabled (GPIO function if implemented)
;
; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
_RDYDIS     EQU    0    ; 0 = READY enabled
                        ; 1 = READY disabled (GPIO function if implemented)
;
; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
; <0=> Active Low  <1=> Active High
_RDYPOL     EQU    0    ; 0 = READY pin is active low
                        ; 1 = READY pin is active high
;
;</h>
;
; <h>Definitions for EBC Mode 1 register EBCMOD1
; ==============================================
;
; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD1.3) <0-15>
_APDIS     EQU    0     ; 0  = Address bus pins 15-1 of PORT1 enabled
                        ; 1  = Pin A15 disabled, A14-1 enabled
                        ; 2  = Pin A15-A14 disabled, A13-1 enabled
                        ; ...
                        ; 15 = Pins A15-A1 disabled
;
; <q> A0PDIS: Address Bit 0 Pin Disable (EBCMOD1.4)
_A0PDIS    EQU    0     ; 0 = Address bus pin 0 of PORT1 enabled
                        ; 1 = Address bus pin 0 of PORT1 enabled
;
; <q> ALPDIS: Address Low Pins Disable (EBCMOD1.5)
_ALPDIS    EQU    0     ; 0 = Address bus pin 7-0 generally enabled
                        ; 1 = Address bus pin 7-0 of PORT1 disabled
;
; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
_DPPDIS    EQU    0     ; 0 = Data bus pins 15-8 of PORT0 enabled
                        ; 1 = Data bus pins 15-8 disabled (used as GPIO)
;
; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
_WRPDIS    EQU    0     ; 0 = WR/WRL pin of Port P20 enabled
                        ; 1 = WR/WRL pin of Port P20 disabled
;
;</h></e>
;
; <e>Configure External Bus Behaviour for CS0 area
; ================================================
;
; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
$SET (CONFIG_CS0 = 0)
;
; <h>Definitions for Function Configuration Register FCONCS0
; =======================================================
;
; <q> ENCS0: Enable Chip Select (FCONCS0.0)
_ENCS0     EQU    1     ; 0 = Chip Select 0 disabled
                        ; 1 = Chip Select 0 enabled
;
; <q> RDYEN0: Ready Enable (FCONCS0.1)
_RDYEN0    EQU    0     ; 0 = Access time controlled by TCONCS0.PHE0
                        ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
;
; <o> RDYMOD0: Ready Mode (FCONCS0.2) 
; <0=> Asynchronous  <1=> Synchronous
_RDYMOD0   EQU    0     ; 0 = Asynchronous READY
                        ; 1 = Synchronous READY
;
; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
; <0=> 8-bit Demultiplexed Bus  <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP0     EQU    2     ; 0 = 8 bit Demultiplexed bus
                        ; 1 = 8 bit Multiplexed bus
                        ; 2 = 16 bit Demultiplexed bus
                        ; 3 = 16 bit Multiplexed bus
; </h>
;
; <h> TCONCS0: Definitions for the Timing Configuration register 
; ==========================================================
;
; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
_PHA0       EQU    0    ; 0 = 0 clock cycles
                        ; : = : 
                        ; 3 = 3 clock cycles
;
; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
_PHB0       EQU    0    ; 0 = 1 clock cycle
                        ; 1 = 2 clock cycles
;
; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
_PHC0       EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
_PHD0       EQU    0    ; 0 = 0 clock cycles
                        ; 1 = 1 clock cycle
;
; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
_PHE0       EQU    8    ; 0 = 1 clock cycle
                        ; : = :
                        ; 31 = 32 clock cycles
;
; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
_RDPHF0     EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
_WRPHF0     EQU    3    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS1 Area
;   =============================================
;
; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
$SET (CONFIG_CS1 = 0)
;
; <h>Definitions for Address Select register ADDRSEL1
; ===================================================
; <o> CS1 Start Address   <0x0-0xFFFFFF:0x1000>
_ADDR1      EQU 0x100000     ; Set CS1# Start Address (default 100000H)

; <o> CS1 Size in KB      
; <4=>    4KB      <8=>    8KB      <16=>   16KB     <32=>   32KB   
; <64=>   64KB     <128=>  128KB    <256=>  256KB    <512=>  512KB
; <1024=> 1024KB   <2048=> 2048KB   <4096=> 4096KB   <8192=> 8192KB
_SIZE1      EQU 1024*KB         ; Set CS1# Size (default 1024*KB = 1*MB)
                             ; possible values for _SIZE1 are:
                             ;    4*KB            (gives RGSZ1 = 0)
                             ;    8*KB            (gives RGSZ1 = 1)
                             ;   16*KB            (gives RGSZ1 = 2)
                             ;   32*KB            (gives RGSZ1 = 3)
                             ;   64*KB            (gives RGSZ1 = 4)
                             ;  128*KB            (gives RGSZ1 = 5)
                             ;  256*KB            (gives RGSZ1 = 6)
                             ;  512*KB            (gives RGSZ1 = 7)
                             ; 1024*KB  or  1*MB  (gives RGSZ1 = 8)
                             ; 2048*KB  or  2*MB  (gives RGSZ1 = 9)
                             ; 4096*KB  or  4*MB  (gives RGSZ1 = 10)
                             ; 8192*KB  or  8*MB  (gives RGSZ1 = 11)
                             ;                    (RGSZ1 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS1
; =======================================================
;
; <q> ENCS1: Enable Chip Select (FCONCS1.0)
_ENCS1     EQU    1     ; 0 = Chip Select 0 disabled
                        ; 1 = Chip Select 0 enabled
;
; <q> RDYEN1: Ready Enable (FCONCS1.1)
_RDYEN1    EQU    0     ; 0 = Access time controlled by TCONCS1.PHE1
                        ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
;
; <o> RDYMOD1: Ready Mode (FCONCS1.2)
; <0=> Asynchronous  <1=> Synchronous