glibc-2.1.3-allow-gcc3-longlong.patch

linux下编译交叉工具链的工具源码

+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\
+	"cas	%0,r2,r0\n"						\
+	"mfs	r10,%1"							\
 	     : "=r" ((USItype)(ph)),					\
 	       "=r" ((USItype)(pl))					\
 	     : "%r" (__m0),						\
@@ -959,9 +959,9 @@
 #if defined (__sh2__) && W_TYPE_SIZE == 32
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
-       "dmulu.l	%2,%3
-	sts	macl,%1
-	sts	mach,%0"						\
+       "dmulu.l	%2,%3\n"						\
+	"sts	macl,%1\n"						\
+	"sts	mach,%0"						\
 	   : "=r" ((USItype)(w1)),					\
 	     "=r" ((USItype)(w0))					\
 	   : "r" ((USItype)(u)),					\
@@ -972,8 +972,8 @@
 
 #if defined (__sparc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("addcc %r4,%5,%1
-	addx %r2,%3,%0"							\
+  __asm__ ("addcc %r4,%5,%1\n"						\
+	"addx %r2,%3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%rJ" ((USItype)(ah)),					\
@@ -982,8 +982,8 @@
 	     "rI" ((USItype)(bl))					\
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("subcc %r4,%5,%1
-	subx %r2,%3,%0"							\
+  __asm__ ("subcc %r4,%5,%1\n"						\
+	"subx %r2,%3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "rJ" ((USItype)(ah)),					\
@@ -1029,45 +1029,45 @@
 	     "r" ((USItype)(v)))
 #define UMUL_TIME 5
 #define udiv_qrnnd(q, r, n1, n0, d) \
-  __asm__ ("! Inlined udiv_qrnnd
-	wr	%%g0,%2,%%y	! Not a delayed write for sparclite
-	tst	%%g0
-	divscc	%3,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%%g1
-	divscc	%%g1,%4,%0
-	rd	%%y,%1
-	bl,a 1f
-	add	%1,%4,%1
-1:	! End of inline udiv_qrnnd"					\
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+	"wr	%%g0,%2,%%y	! Not a delayed write for sparclite\n"	\
+	"tst	%%g0\n"							\
+	"divscc	%3,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%%g1\n"						\
+	"divscc	%%g1,%4,%0\n"						\
+	"rd	%%y,%1\n"						\
+	"bl,a 1f\n"							\
+	"add	%1,%4,%1\n"						\
+"1:	! End of inline udiv_qrnnd"					\
 	   : "=r" ((USItype)(q)),					\
 	     "=r" ((USItype)(r))					\
 	   : "r" ((USItype)(n1)),					\
@@ -1087,46 +1087,46 @@
 /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd.  */
 #ifndef umul_ppmm
 #define umul_ppmm(w1, w0, u, v) \
-  __asm__ ("! Inlined umul_ppmm
-	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr
-	sra	%3,31,%%g2	! Don't move this insn
-	and	%2,%%g2,%%g2	! Don't move this insn
-	andcc	%%g0,0,%%g1	! Don't move this insn
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,%3,%%g1
-	mulscc	%%g1,0,%%g1
-	add	%%g1,%%g2,%0
-	rd	%%y,%1"							\
+  __asm__ ("! Inlined umul_ppmm\n"					\
+	"wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr\n" \
+	"sra	%3,31,%%g2	! Don't move this insn\n"		\
+	"and	%2,%%g2,%%g2	! Don't move this insn\n"		\
+	"andcc	%%g0,0,%%g1	! Don't move this insn\n"		\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,%3,%%g1\n"						\
+	"mulscc	%%g1,0,%%g1\n"						\
+	"add	%%g1,%%g2,%0\n"						\
+	"rd	%%y,%1"							\
 	   : "=r" ((USItype)(w1)),					\
 	     "=r" ((USItype)(w0))					\
 	   : "%rI" ((USItype)(u)),					\
@@ -1138,30 +1138,30 @@
 /* It's quite necessary to add this much assembler for the sparc.
    The default udiv_qrnnd (in C) is more than 10 times slower!  */
 #define udiv_qrnnd(q, r, n1, n0, d) \
-  __asm__ ("! Inlined udiv_qrnnd
-	mov	32,%%g1
-	subcc	%1,%2,%%g0
-1:	bcs	5f
-	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb
-	sub	%1,%2,%1	! this kills msb of n
-	addx	%1,%1,%1	! so this can't give carry
-	subcc	%%g1,1,%%g1
-2:	bne	1b
-	 subcc	%1,%2,%%g0
-	bcs	3f
-	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb
-	b	3f
-	 sub	%1,%2,%1	! this kills msb of n
-4:	sub	%1,%2,%1
-5:	addxcc	%1,%1,%1
-	bcc	2b
-	 subcc	%%g1,1,%%g1
-! Got carry from n.  Subtract next step to cancel this carry.
-	bne	4b
-	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb
-	sub	%1,%2,%1
-3:	xnor	%0,0,%0
-	! End of inline udiv_qrnnd"					\
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+	"mov	32,%%g1\n"						\
+	"subcc	%1,%2,%%g0\n"						\
+"1:	bcs	5f\n"							\
+	"addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+	"sub	%1,%2,%1	! this kills msb of n\n"		\
+	"addx	%1,%1,%1	! so this can't give carry\n"		\
+	"subcc	%%g1,1,%%g1\n"						\
+"2:	bne	1b\n"							\
+	"subcc	%1,%2,%%g0\n"						\
+	"bcs	3f\n"							\
+	"addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+	"b	3f\n"							\
+	"sub	%1,%2,%1	! this kills msb of n\n"		\
+"4:	sub	%1,%2,%1\n"						\
+"5:	addxcc	%1,%1,%1\n"						\
+	"bcc	2b\n"							\
+	"subcc	%%g1,1,%%g1\n"						\
+"! Got carry from n.  Subtract next step to cancel this carry.\n"	\
+	"bne	4b\n"							\
+	"addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb\n"	\
+	"sub	%1,%2,%1\n"						\
+"3:	xnor	%0,0,%0\n"						\
+	"! End of inline udiv_qrnnd"					\
 	   : "=&r" ((USItype)(q)),					\
 	     "=&r" ((USItype)(r))					\
 	   : "r" ((USItype)(d)),					\
@@ -1179,11 +1179,11 @@
 #if (defined (__sparc_v9__) || (defined (__sparc__) && defined (__arch64__)) \
     || defined (__sparcv9)) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl)				\
-  __asm__ ("addcc %r4,%5,%1
-  	    add %r2,%3,%0
-  	    bcs,a,pn %%xcc, 1f
-  	    add %0, 1, %0
-  	    1:"								\
+  __asm__ ("addcc %r4,%5,%1\n"						\
+  	    "add %r2,%3,%0\n"						\
+  	    "bcs,a,pn %%xcc, 1f\n"					\
+  	    "add %0, 1, %0\n"						\
+  	    "1:"							\
 	   : "=r" ((UDItype)(sh)),				      	\
 	     "=&r" ((UDItype)(sl))				      	\
 	   : "r" ((UDItype)(ah)),				     	\
@@ -1193,11 +1193,11 @@
 	   : "cc")
 
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) 				\
-  __asm__ ("subcc %r4,%5,%1
-  	    sub %r2,%3,%0
-  	    bcs,a,pn %%xcc, 1f
-  	    sub %0, 1, %0
-  	    1:"								\
+  __asm__ ("subcc %r4,%5,%1\n"						\
+  	    "sub %r2,%3,%0\n"						\
+  	    "bcs,a,pn %%xcc, 1f\n"					\
+  	    "sub %0, 1, %0\n"						\
+  	    "1:"							\
 	   : "=r" ((UDItype)(sh)),				      	\
 	     "=&r" ((UDItype)(sl))				      	\
 	   : "r" ((UDItype)(ah)),				     	\
@@ -1210,27 +1210,27 @@
   do {									\
 	  UDItype tmp1, tmp2, tmp3, tmp4;				\
 	  __asm__ __volatile__ (					\
-		   "srl %7,0,%3
-		    mulx %3,%6,%1
-		    srlx %6,32,%2
-		    mulx %2,%3,%4
-		    sllx %4,32,%5
-		    srl %6,0,%3
-		    sub %1,%5,%5
-		    srlx %5,32,%5
-		    addcc %4,%5,%4
-		    srlx %7,32,%5
-		    mulx %3,%5,%3
-		    mulx %2,%5,%5
-		    sethi %%hi(0x80000000),%2
-		    addcc %4,%3,%4
-		    srlx %4,32,%4
-		    add %2,%2,%2
-		    movcc %%xcc,%%g0,%2
-		    addcc %5,%4,%5
-		    sllx %3,32,%3
-		    add %1,%3,%1
-		    add %5,%2,%0"					\
+		   "srl %7,0,%3\n"					\
+		    "mulx %3,%6,%1\n"					\
+		    "srlx %6,32,%2\n"					\
+		    "mulx %2,%3,%4\n"					\
+		    "sllx %4,32,%5\n"					\
+		    "srl %6,0,%3\n"					\
+		    "sub %1,%5,%5\n"					\
+		    "srlx %5,32,%5\n"					\
+		    "addcc %4,%5,%4\n"					\
+		    "srlx %7,32,%5\n"					\
+		    "mulx %3,%5,%3\n"					\
+		    "mulx %2,%5,%5\n"					\
+		    "sethi %%hi(0x80000000),%2\n"			\
+		    "addcc %4,%3,%4\n"					\
+		    "srlx %4,32,%4\n"					\
+		    "add %2,%2,%2\n"					\
+		    "movcc %%xcc,%%g0,%2\n"				\
+		    "addcc %5,%4,%5\n"					\
+		    "sllx %3,32,%3\n"					\
+		    "add %1,%3,%1\n"					\
+		    "add %5,%2,%0"					\
 	   : "=r" ((UDItype)(wh)),					\
 	     "=&r" ((UDItype)(wl)),					\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
@@ -1244,8 +1244,8 @@
 
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("addl2 %5,%1
-	adwc %3,%0"							\
+  __asm__ ("addl2 %5,%1\n"						\
+	"adwc %3,%0"							\
 	   : "=g" ((USItype)(sh)),					\
 	     "=&g" ((USItype)(sl))					\
 	   : "%0" ((USItype)(ah)),					\
@@ -1253,8 +1253,8 @@
 	     "%1" ((USItype)(al)),					\
 	     "g" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("subl2 %5,%1
-	sbwc %3,%0"							\
+  __asm__ ("subl2 %5,%1\n"						\
+	"sbwc %3,%0"							\
 	   : "=g" ((USItype)(sh)),					\
 	     "=&g" ((USItype)(sl))					\
 	   : "0" ((USItype)(ah)),					\