glibc-2.1.3-allow-gcc3-longlong.patch

linux下编译交叉工具链的工具源码

--- glibc-2.1.3/stdlib/longlong.h.old	2004-03-05 14:49:14.000000000 -0800
+++ glibc-2.1.3/stdlib/longlong.h	2004-03-05 15:19:26.000000000 -0800
@@ -106,8 +106,8 @@
 
 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("add %1,%4,%5
-	addc %0,%2,%3"							\
+  __asm__ ("add %1,%4,%5\n"						\
+	"addc %0,%2,%3"							\
 	   : "=r" ((USItype)(sh)),					\
 	    "=&r" ((USItype)(sl))					\
 	   : "%r" ((USItype)(ah)),					\
@@ -115,8 +115,8 @@
 	     "%r" ((USItype)(al)),					\
 	     "rI" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("sub %1,%4,%5
-	subc %0,%2,%3"							\
+  __asm__ ("sub %1,%4,%5\n"						\
+	"subc %0,%2,%3"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "r" ((USItype)(ah)),					\
@@ -173,8 +173,8 @@
 
 #if defined (__arm__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("adds	%1, %4, %5
-	adc	%0, %2, %3"						\
+  __asm__ ("adds	%1, %4, %5\n"					\
+	"adc	%0, %2, %3"						\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%r" ((USItype)(ah)),					\
@@ -182,8 +182,8 @@
 	     "%r" ((USItype)(al)),					\
 	     "rI" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("subs	%1, %4, %5
-	sbc	%0, %2, %3"						\
+  __asm__ ("subs	%1, %4, %5\n"					\
+	"sbc	%0, %2, %3"						\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "r" ((USItype)(ah)),					\
@@ -192,19 +192,19 @@
 	     "rI" ((USItype)(bl)))
 #if 0
 #define umul_ppmm(xh, xl, a, b) \
-  __asm__ ("%@ Inlined umul_ppmm
-	mov	%|r0, %2, lsr #16
-	mov	%|r2, %3, lsr #16
-	bic	%|r1, %2, %|r0, lsl #16
-	bic	%|r2, %3, %|r2, lsl #16
-	mul	%1, %|r1, %|r2
-	mul	%|r2, %|r0, %|r2
-	mul	%|r1, %0, %|r1
-	mul	%0, %|r0, %0
-	adds	%|r1, %|r2, %|r1
-	addcs	%0, %0, #65536
-	adds	%1, %1, %|r1, lsl #16
-	adc	%0, %0, %|r1, lsr #16"					\
+  __asm__ ("%@ Inlined umul_ppmm\n"					\
+	"mov	%|r0, %2, lsr #16\n"					\
+	"mov	%|r2, %3, lsr #16\n"					\
+	"bic	%|r1, %2, %|r0, lsl #16\n"				\
+	"bic	%|r2, %3, %|r2, lsl #16\n"				\
+	"mul	%1, %|r1, %|r2\n"					\
+	"mul	%|r2, %|r0, %|r2\n"					\
+	"mul	%|r1, %0, %|r1\n"					\
+	"mul	%0, %|r0, %0\n"						\
+	"adds	%|r1, %|r2, %|r1\n"					\
+	"addcs	%0, %0, #65536\n"					\
+	"adds	%1, %1, %|r1, lsl #16\n"				\
+	"adc	%0, %0, %|r1, lsr #16"					\
 	   : "=&r" ((USItype)(xh)),					\
 	     "=r" ((USItype)(xl))					\
 	   : "r" ((USItype)(a)),					\
@@ -245,8 +245,8 @@
 
 #if defined (__gmicro__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("add.w %5,%1
-	addx %3,%0"							\
+  __asm__ ("add.w %5,%1\n"						\
+	"addx %3,%0"							\
 	   : "=g" ((USItype)(sh)),					\
 	     "=&g" ((USItype)(sl))					\
 	   : "%0" ((USItype)(ah)),					\
@@ -254,8 +254,8 @@
 	     "%1" ((USItype)(al)),					\
 	     "g" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("sub.w %5,%1
-	subx %3,%0"							\
+  __asm__ ("sub.w %5,%1\n"						\
+	"subx %3,%0"							\
 	   : "=g" ((USItype)(sh)),					\
 	     "=&g" ((USItype)(sl))					\
 	   : "0" ((USItype)(ah)),					\
@@ -284,8 +284,8 @@
 
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("add %4,%5,%1
-	addc %2,%3,%0"							\
+  __asm__ ("add %4,%5,%1\n"						\
+	"addc %2,%3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%rM" ((USItype)(ah)),					\
@@ -293,8 +293,8 @@
 	     "%rM" ((USItype)(al)),					\
 	     "rM" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("sub %4,%5,%1
-	subb %2,%3,%0"							\
+  __asm__ ("sub %4,%5,%1\n"						\
+	"subb %2,%3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "rM" ((USItype)(ah)),					\
@@ -332,22 +332,22 @@
   do {									\
     USItype __tmp;							\
     __asm__ (								\
-       "ldi		1,%0
-	extru,=		%1,15,16,%%r0		; Bits 31..16 zero?
-	extru,tr	%1,15,16,%1		; No.  Shift down, skip add.
-	ldo		16(%0),%0		; Yes.  Perform add.
-	extru,=		%1,23,8,%%r0		; Bits 15..8 zero?
-	extru,tr	%1,23,8,%1		; No.  Shift down, skip add.
-	ldo		8(%0),%0		; Yes.  Perform add.
-	extru,=		%1,27,4,%%r0		; Bits 7..4 zero?
-	extru,tr	%1,27,4,%1		; No.  Shift down, skip add.
-	ldo		4(%0),%0		; Yes.  Perform add.
-	extru,=		%1,29,2,%%r0		; Bits 3..2 zero?
-	extru,tr	%1,29,2,%1		; No.  Shift down, skip add.
-	ldo		2(%0),%0		; Yes.  Perform add.
-	extru		%1,30,1,%1		; Extract bit 1.
-	sub		%0,%1,%0		; Subtract it.
-	" : "=r" (count), "=r" (__tmp) : "1" (x));			\
+       "ldi		1,%0\n"						\
+	"extru,=	%1,15,16,%%r0		; Bits 31..16 zero?\n"			\
+	"extru,tr	%1,15,16,%1		; No.  Shift down, skip add.\n"		\
+	"ldo		16(%0),%0		; Yes.  Perform add.\n"			\
+	"extru,=	%1,23,8,%%r0		; Bits 15..8 zero?\n"			\
+	"extru,tr	%1,23,8,%1		; No.  Shift down, skip add.\n"		\
+	"ldo		8(%0),%0		; Yes.  Perform add.\n"			\
+	"extru,=	%1,27,4,%%r0		; Bits 7..4 zero?\n"			\
+	"extru,tr	%1,27,4,%1		; No.  Shift down, skip add.\n"		\
+	"ldo		4(%0),%0		; Yes.  Perform add.\n"			\
+	"extru,=	%1,29,2,%%r0		; Bits 3..2 zero?\n"			\
+	"extru,tr	%1,29,2,%1		; No.  Shift down, skip add.\n"		\
+	"ldo		2(%0),%0		; Yes.  Perform add.\n"			\
+	"extru		%1,30,1,%1		; Extract bit 1.\n"			\
+	"sub		%0,%1,%0		; Subtract it.\n"			\
+	: "=r" (count), "=r" (__tmp) : "1" (x));			\
   } while (0)
 #endif /* hppa */
 
@@ -394,8 +394,8 @@
 
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("addl %5,%1
-	adcl %3,%0"							\
+  __asm__ ("addl %5,%1\n"						\
+	"adcl %3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%0" ((USItype)(ah)),					\
@@ -403,8 +403,8 @@
 	     "%1" ((USItype)(al)),					\
 	     "g" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("subl %5,%1
-	sbbl %3,%0"							\
+  __asm__ ("subl %5,%1\n"						\
+	"sbbl %3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "0" ((USItype)(ah)),					\
@@ -516,8 +516,8 @@
 
 #if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("add%.l %5,%1
-	addx%.l %3,%0"							\
+  __asm__ ("add%.l %5,%1\n"						\
+	"addx%.l %3,%0"							\
 	   : "=d" ((USItype)(sh)),					\
 	     "=&d" ((USItype)(sl))					\
 	   : "%0" ((USItype)(ah)),					\
@@ -525,8 +525,8 @@
 	     "%1" ((USItype)(al)),					\
 	     "g" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("sub%.l %5,%1
-	subx%.l %3,%0"							\
+  __asm__ ("sub%.l %5,%1\n"						\
+	"subx%.l %3,%0"							\
 	   : "=d" ((USItype)(sh)),					\
 	     "=&d" ((USItype)(sl))					\
 	   : "0" ((USItype)(ah)),					\
@@ -564,28 +564,28 @@
 #else /* not mc68020 */
 #define umul_ppmm(xh, xl, a, b) \
   do { USItype __umul_tmp1, __umul_tmp2;				\
-	__asm__ ("| Inlined umul_ppmm
-	move%.l	%5,%3
-	move%.l	%2,%0
-	move%.w	%3,%1
-	swap	%3
-	swap	%0
-	mulu	%2,%1
-	mulu	%3,%0
-	mulu	%2,%3
-	swap	%2
-	mulu	%5,%2
-	add%.l	%3,%2
-	jcc	1f
-	add%.l	%#0x10000,%0
-1:	move%.l	%2,%3
-	clr%.w	%2
-	swap	%2
-	swap	%3
-	clr%.w	%3
-	add%.l	%3,%1
-	addx%.l	%2,%0
-	| End inlined umul_ppmm"					\
+	__asm__ ("| Inlined umul_ppmm\n"				\
+	"move%.l	%5,%3\n"					\
+	"move%.l	%2,%0\n"					\
+	"move%.w	%3,%1\n"					\
+	"swap	%3\n"							\
+	"swap	%0\n"							\
+	"mulu	%2,%1\n"						\
+	"mulu	%3,%0\n"						\
+	"mulu	%2,%3\n"						\
+	"swap	%2\n"							\
+	"mulu	%5,%2\n"						\
+	"add%.l	%3,%2\n"						\
+	"jcc	1f\n"							\
+	"add%.l	%#0x10000,%0\n"						\
+"1:	move%.l	%2,%3\n"						\
+	"clr%.w	%2\n"							\
+	"swap	%2\n"							\
+	"swap	%3\n"							\
+	"clr%.w	%3\n"							\
+	"add%.l	%3,%1\n"						\
+	"addx%.l	%2,%0\n"					\
+	"| End inlined umul_ppmm"					\
 	      : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)),		\
 		"=d" (__umul_tmp1), "=&d" (__umul_tmp2)			\
 	      : "%2" ((USItype)(a)), "d" ((USItype)(b)));		\
@@ -597,8 +597,8 @@
 
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("addu.co %1,%r4,%r5
-	addu.ci %0,%r2,%r3"						\
+  __asm__ ("addu.co %1,%r4,%r5\n"					\
+	"addu.ci %0,%r2,%r3"						\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%rJ" ((USItype)(ah)),					\
@@ -606,8 +606,8 @@
 	     "%rJ" ((USItype)(al)),					\
 	     "rJ" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("subu.co %1,%r4,%r5
-	subu.ci %0,%r2,%r3"						\
+  __asm__ ("subu.co %1,%r4,%r5\n"					\
+	"subu.ci %0,%r2,%r3"						\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "rJ" ((USItype)(ah)),					\
@@ -665,9 +665,9 @@
 	     "d" ((USItype)(v)))
 #else
 #define umul_ppmm(w1, w0, u, v) \
-  __asm__ ("multu %2,%3
-	mflo %0
-	mfhi %1"							\
+  __asm__ ("multu %2,%3\n"						\
+	"mflo %0\n"							\
+	"mfhi %1"							\
 	   : "=d" ((USItype)(w0)),					\
 	     "=d" ((USItype)(w1))					\
 	   : "d" ((USItype)(u)),					\
@@ -687,9 +687,9 @@
 	     "d" ((UDItype)(v)))
 #else
 #define umul_ppmm(w1, w0, u, v) \
-  __asm__ ("dmultu %2,%3
-	mflo %0
-	mfhi %1"							\
+  __asm__ ("dmultu %2,%3\n"						\
+	"mflo %0\n"							\
+	"mfhi %1"							\
 	   : "=d" ((UDItype)(w0)),					\
 	     "=d" ((UDItype)(w1))					\
 	   : "d" ((UDItype)(u)),					\
@@ -857,8 +857,8 @@
 
 #if defined (__pyr__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("addw	%5,%1
-	addwc	%3,%0"							\
+  __asm__ ("addw	%5,%1\n"					\
+	"addwc	%3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%0" ((USItype)(ah)),					\
@@ -866,8 +866,8 @@
 	     "%1" ((USItype)(al)),					\
 	     "g" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("subw	%5,%1
-	subwb	%3,%0"							\
+  __asm__ ("subw	%5,%1\n"					\
+	"subwb	%3,%0"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "0" ((USItype)(ah)),					\
@@ -879,8 +879,8 @@
   ({union {UDItype __ll;						\
 	   struct {USItype __h, __l;} __i;				\
 	  } __xx;							\
-  __asm__ ("movw %1,%R0
-	uemul %2,%0"							\
+  __asm__ ("movw %1,%R0\n"						\
+	"uemul %2,%0"							\
 	   : "=&r" (__xx.__ll)						\
 	   : "g" ((USItype) (u)),					\
 	     "g" ((USItype)(v)));					\
@@ -889,8 +889,8 @@
 
 #if defined (__ibm032__) /* RT/ROMP */  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
-  __asm__ ("a %1,%5
-	ae %0,%3"							\
+  __asm__ ("a %1,%5\n"							\
+	"ae %0,%3"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "%0" ((USItype)(ah)),					\
@@ -898,8 +898,8 @@
 	     "%1" ((USItype)(al)),					\
 	     "r" ((USItype)(bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
-  __asm__ ("s %1,%5
-	se %0,%3"							\
+  __asm__ ("s %1,%5\n"							\
+	"se %0,%3"							\
 	   : "=r" ((USItype)(sh)),					\
 	     "=&r" ((USItype)(sl))					\
 	   : "0" ((USItype)(ah)),					\
@@ -910,26 +910,26 @@
   do {									\
     USItype __m0 = (m0), __m1 = (m1);					\
     __asm__ (								\
-       "s	r2,r2
-	mts	r10,%2
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	m	r2,%3
-	cas	%0,r2,r0
-	mfs	r10,%1"							\
+       "s	r2,r2\n"						\
+	"mts	r10,%2\n"						\
+	"m	r2,%3\n"						\
+	"m	r2,%3\n"						\