📄 pentiumalib.html
字号:
<html><head><!-- /vobs/wpwr/docs/vxworks/ref/pentiumALib.html - generated by refgen from ../i86/pentiumALib.s --> <title> pentiumALib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference : OS Libraries</i></a></p></blockquote><h1>pentiumALib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumALib</strong> - Pentium and PentiumPro specific routines </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./pentiumALib.html#pentiumCr4Get">pentiumCr4Get</a>( )</b> - get contents of CR4 register<br><b><a href="./pentiumALib.html#pentiumCr4Set">pentiumCr4Set</a>( )</b> - sets specified value to the CR4 register<br><b><a href="./pentiumALib.html#pentiumP6PmcStart">pentiumP6PmcStart</a>( )</b> - start both PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP6PmcStop">pentiumP6PmcStop</a>( )</b> - stop both PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP6PmcStop1">pentiumP6PmcStop1</a>( )</b> - stop PMC1<br><b><a href="./pentiumALib.html#pentiumP6PmcGet">pentiumP6PmcGet</a>( )</b> - get the contents of PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP6PmcGet0">pentiumP6PmcGet0</a>( )</b> - get the contents of PMC0<br><b><a href="./pentiumALib.html#pentiumP6PmcGet1">pentiumP6PmcGet1</a>( )</b> - get the contents of PMC1<br><b><a href="./pentiumALib.html#pentiumP6PmcReset">pentiumP6PmcReset</a>( )</b> - reset both PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP6PmcReset0">pentiumP6PmcReset0</a>( )</b> - reset PMC0<br><b><a href="./pentiumALib.html#pentiumP6PmcReset1">pentiumP6PmcReset1</a>( )</b> - reset PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcStart0">pentiumP5PmcStart0</a>( )</b> - start PMC0<br><b><a href="./pentiumALib.html#pentiumP5PmcStart1">pentiumP5PmcStart1</a>( )</b> - start PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcStop">pentiumP5PmcStop</a>( )</b> - stop both P5 PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcStop0">pentiumP5PmcStop0</a>( )</b> - stop P5 PMC0<br><b><a href="./pentiumALib.html#pentiumP5PmcStop1">pentiumP5PmcStop1</a>( )</b> - stop P5 PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcGet">pentiumP5PmcGet</a>( )</b> - get the contents of P5 PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcGet0">pentiumP5PmcGet0</a>( )</b> - get the contents of P5 PMC0<br><b><a href="./pentiumALib.html#pentiumP5PmcGet1">pentiumP5PmcGet1</a>( )</b> - get the contents of P5 PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcReset">pentiumP5PmcReset</a>( )</b> - reset both PMC0 and PMC1<br><b><a href="./pentiumALib.html#pentiumP5PmcReset0">pentiumP5PmcReset0</a>( )</b> - reset PMC0<br><b><a href="./pentiumALib.html#pentiumP5PmcReset1">pentiumP5PmcReset1</a>( )</b> - reset PMC1<br><b><a href="./pentiumALib.html#pentiumTscGet64">pentiumTscGet64</a>( )</b> - get 64Bit TSC (Timestamp Counter)<br><b><a href="./pentiumALib.html#pentiumTscGet32">pentiumTscGet32</a>( )</b> - get the lower half of the 64Bit TSC (Timestamp Counter)<br><b><a href="./pentiumALib.html#pentiumTscReset">pentiumTscReset</a>( )</b> - reset the TSC (Timestamp Counter)<br><b><a href="./pentiumALib.html#pentiumMsrGet">pentiumMsrGet</a>( )</b> - get the contents of the specified MSR (Model Specific Register)<br><b><a href="./pentiumALib.html#pentiumMsrSet">pentiumMsrSet</a>( )</b> - set a value to the specified MSR (Model Specific Registers)<br><b><a href="./pentiumALib.html#pentiumTlbFlush">pentiumTlbFlush</a>( )</b> - flush TLBs (Translation Lookaside Buffers)<br><b><a href="./pentiumALib.html#pentiumSerialize">pentiumSerialize</a>( )</b> - execute a serializing instruction CPUID<br><b><a href="./pentiumALib.html#pentiumBts">pentiumBts</a>( )</b> - execute atomic compare-and-exchange instruction to set a bit<br><b><a href="./pentiumALib.html#pentiumBtc">pentiumBtc</a>( )</b> - execute atomic compare-and-exchange instruction to clear a bit<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This module contains Pentium and PentiumPro specific routines written in assembly language.<p></blockQuote><h4>MCA (Machine Check Architecture)</h4><blockQuote>The Pentium processor introduced a new exception called the machine-check exception (interrupt-18). This exception is used to signal hardware-relatederrors, such as a parity error on a read cycle. The PentiumPro processorextends the types of errors that can be detected and that generate a machine-check exception. It also provides a new machine-check architecture thatrecords information about a machine-check error and provides the basis for anextended error logging capability.<p>MCA is enabled and its status registers are cleared zero in <b><a href="./sysLib.html#sysHwInit">sysHwInit</a>( )</b>.Its registers are accessed by <b><a href="./pentiumALib.html#pentiumMsrSet">pentiumMsrSet</a>( )</b> and <b><a href="./pentiumALib.html#pentiumMsrGet">pentiumMsrGet</a>( )</b>.<p></blockQuote><h4>PMC (Performance Monitoring Counters)</h4><blockQuote>The P5 and P6 family of processor has two performance-monitoring counters foruse in monitoring internal hardware operations. These counters are durationor event counters that can be programmed to count any of approximately 100different types of events, such as the number of instructions decoded, numberof interrupts received, or number of cache loads. However, the set of eventscan be counted with PMC is different in the P5 and P6 family of processors;and the locations and bit difinitions of the related counter and controlregisters are also different. So there are two set of PMC routines, one forP6 family and one for p5 family respectively.<p>There are nine routines to interface the PMC of P6 family processors. Thesenine routines are:<pre> STATUS pentiumP6PmcStart ( int pmcEvtSel0; /* performance event select register 0 */ int pmcEvtSel1; /* performance event select register 1 */ ) void pentiumP6PmcStop (void) void pentiumP6PmcStop1 (void) void pentiumP6PmcGet ( long long int * pPmc0; /* performance monitoring counter 0 */ long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP6PmcGet0 ( long long int * pPmc0; /* performance monitoring counter 0 */ ) void pentiumP6PmcGet1 ( long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP6PmcReset (void) void pentiumP6PmcReset0 (void) void pentiumP6PmcReset1 (void)</pre><b><a href="./pentiumALib.html#pentiumP6PmcStart">pentiumP6PmcStart</a>( )</b> starts both PMC0 and PMC1. <b><a href="./pentiumALib.html#pentiumP6PmcStop">pentiumP6PmcStop</a>( )</b> stops them, and <b><a href="./pentiumALib.html#pentiumP6PmcStop1">pentiumP6PmcStop1</a>( )</b> stops only PMC1. <b><a href="./pentiumALib.html#pentiumP6PmcGet">pentiumP6PmcGet</a>( )</b> gets contents of PMC0 and PMC1. <b><a href="./pentiumALib.html#pentiumP6PmcGet0">pentiumP6PmcGet0</a>( )</b> getscontents of PMC0, and <b><a href="./pentiumALib.html#pentiumP6PmcGet1">pentiumP6PmcGet1</a>( )</b> gets contents of PMC1.<b><a href="./pentiumALib.html#pentiumP6PmcReset">pentiumP6PmcReset</a>( )</b> resets both PMC0 and PMC1. <b><a href="./pentiumALib.html#pentiumP6PmcReset0">pentiumP6PmcReset0</a>( )</b> resetsPMC0, and <b><a href="./pentiumALib.html#pentiumP6PmcReset1">pentiumP6PmcReset1</a>( )</b> resets PMC1.PMC is enabled in <b><a href="./sysLib.html#sysHwInit">sysHwInit</a>( )</b>. Selected events in the default configurationare PMC0 = number of hardware interrupts received and PMC1 = number of misaligned data memory references.<p>There are ten routines to interface the PMC of P5 family processors. Theseten routines are:<pre> STATUS pentiumP5PmcStart0 ( int pmc0Cesr; /* PMC0 control and event select */ ) STATUS pentiumP5PmcStart1 ( int pmc1Cesr; /* PMC1 control and event select */ ) void pentiumP5PmcStop0 (void) void pentiumP5PmcStop1 (void) void pentiumP5PmcGet ( long long int * pPmc0; /* performance monitoring counter 0 */ long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP5PmcGet0 ( long long int * pPmc0; /* performance monitoring counter 0 */ ) void pentiumP5PmcGet1 ( long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP5PmcReset (void) void pentiumP5PmcReset0 (void) void pentiumP5PmcReset1 (void)</pre><b><a href="./pentiumALib.html#pentiumP5PmcStart0">pentiumP5PmcStart0</a>( )</b> starts PMC0, and <b><a href="./pentiumALib.html#pentiumP5PmcStart1">pentiumP5PmcStart1</a>( )</b> starts PMC1. <b><a href="./pentiumALib.html#pentiumP5PmcStop0">pentiumP5PmcStop0</a>( )</b> stops PMC0, and <b><a href="./pentiumALib.html#pentiumP5PmcStop1">pentiumP5PmcStop1</a>( )</b> stops PMC1. <b><a href="./pentiumALib.html#pentiumP5PmcGet">pentiumP5PmcGet</a>( )</b> gets contents of PMC0 and PMC1. <b><a href="./pentiumALib.html#pentiumP5PmcGet0">pentiumP5PmcGet0</a>( )</b> getscontents of PMC0, and <b><a href="./pentiumALib.html#pentiumP5PmcGet1">pentiumP5PmcGet1</a>( )</b> gets contents of PMC1.<b><a href="./pentiumALib.html#pentiumP5PmcReset">pentiumP5PmcReset</a>( )</b> resets both PMC0 and PMC1. <b><a href="./pentiumALib.html#pentiumP5PmcReset0">pentiumP5PmcReset0</a>( )</b> resetsPMC0, and <b><a href="./pentiumALib.html#pentiumP5PmcReset1">pentiumP5PmcReset1</a>( )</b> resets PMC1.PMC is enabled in <b><a href="./sysLib.html#sysHwInit">sysHwInit</a>( )</b>. Selected events in the default configurationare PMC0 = number of hardware interrupts received and PMC1 = number of misaligned data memory references.<p></blockQuote><h4>MSR (Model Specific Register)</h4><blockQuote>The concept of model-specific registers (MSRs) to control hardware functionsin the processor or to monitor processor activity was introduced in the PentiumPro processor. The new registers control the debug extensions, the performance counters, the machine-check exception capability, the machinecheck architecture, and the MTRRs. The MSRs can be read and written to usingthe RDMSR and WRMSR instructions, respectively.<p>There are two routines to interface the MSR. These two routines are:<pre> void pentiumMsrGet ( int address, /* MSR address */ long long int * pData /* MSR data */ ) void pentiumMsrSet ( int address, /* MSR address */ long long int * pData /* MSR data */ )</pre><b><a href="./pentiumALib.html#pentiumMsrGet">pentiumMsrGet</a>( )</b> get contents of the specified MSR, and <b><a href="./pentiumALib.html#pentiumMsrSet">pentiumMsrSet</a>( )</b> sets value to the specified MSR.<p></blockQuote><h4>TSC (Time Stamp Counter)</h4><blockQuote>The PentiumPro processor provides a 64-bit time-stamp counter that is incremented every processor clock cycle. The counter is incremented evenwhen the processor is halted by the HLT instruction or the external STPCLK#pin. The time-stamp counter is set to 0 following a hardware reset of theprocessor. The RDTSC instruction reads the time stamp counter and is guaranteed to return a monotonically increasing unique value whenever executed, except for 64-bit counter wraparound. Intel guarantees, architecturally, that the time-stamp counter frequency and configuration willbe such that it will not wraparound within 10 years after being reset to 0.The period for counter wrap is several thousands of years in the PentiumProand Pentium processors.<p>There are three routines to interface the TSC. These three routines are:<pre> void pentiumTscReset (void) void pentiumTscGet32 (void) void pentiumTscGet64 ( long long int * pTsc /* TSC */ )</pre><b><a href="./pentiumALib.html#pentiumTscReset">pentiumTscReset</a>( )</b> resets the TSC. <b><a href="./pentiumALib.html#pentiumTscGet32">pentiumTscGet32</a>( )</b> gets the lower half of the64Bit TSC, and <b><a href="./pentiumALib.html#pentiumTscGet64">pentiumTscGet64</a>( )</b> gets the entire 64Bit TSC.<p>Four other routines are provided in this library. They are:<pre> void pentiumTlbFlush (void) void pentiumSerialize (void) STATUS pentiumBts ( char * pFlag /* flag address */ ) STATUS pentiumBtc (pFlag) ( char * pFlag /* flag address */ )</pre><b><a href="./pentiumALib.html#pentiumTlbFlush">pentiumTlbFlush</a>( )</b> flushes TLBs (Translation Lookaside Buffers). <b><a href="./pentiumALib.html#pentiumSerialize">pentiumSerialize</a>( )</b> does serialization by executing CPUID instruction.<b><a href="./pentiumALib.html#pentiumBts">pentiumBts</a>( )</b> executes an atomic compare-and-exchange instruction to set a bit.<b><a href="./pentiumALib.html#pentiumBtc">pentiumBtc</a>( )</b> executes an atomic compare-and-exchange instruction to clear a bit.<p></blockquote><h4>SEE ALSO</h4><blockquote><p><p><i>Pentium, PentiumPro Family Developer's Manual </i><hr><a name="pentiumCr4Get"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumCr4Get( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumCr4Get( )</strong> - get contents of CR4 register</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>int pentiumCr4Get (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p><p>This routine gets the contents of the CR4 register.<p></blockquote><h4>RETURNS</h4><blockquote><p>Contents of CR4 register.<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumALib.html#top">pentiumALib</a></b><hr><a name="pentiumCr4Set"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumCr4Set( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumCr4Set( )</strong> - sets specified value to the CR4 register</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void pentiumCr4Set (cr4) int cr4; /* value to write CR4 register */</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p><p>This routine sets a specified value to the CR4 register.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumALib.html#top">pentiumALib</a></b><hr><a name="pentiumP6PmcStart"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumP6PmcStart( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumP6PmcStart( )</strong> - start both PMC0 and PMC1</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS pentiumP6PmcStart (pmcEvtSel0, pmcEvtSel1) int pmcEvtSel0; /* Performance Event Select Register 0 */ int pmcEvtSel1; /* Performance Event Select Register 1 */</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p><p>This routine starts both PMC0 (Performance Monitoring Counter 0) and PMC1by writing specified events to Performance Event Select Registers. The first parameter is a content of Performance Event Select Register 0,and the second parameter is for the Performance Event Select Register 1.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK or ERROR if PMC is already started.<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumALib.html#top">pentiumALib</a></b><hr><a name="pentiumP6PmcStop"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumP6PmcStop( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumP6PmcStop( )</strong> - stop both PMC0 and PMC1</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void pentiumP6PmcStop (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p><p>This routine stops both PMC0 (Performance Monitoring Counter 0) and PMC1by clearing two Performance Event Select Registers.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumALib.html#top">pentiumALib</a></b><hr><a name="pentiumP6PmcStop1"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumP6PmcStop1( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumP6PmcStop1( )</strong> - stop PMC1</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void pentiumP6PmcStop1 (void)</pre>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -