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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/fppArchLib.html - generated by refgen from fppArchLib.c --> <title> fppArchLib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference : OS Libraries</i></a></p></blockquote><h1>fppArchLib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>fppArchLib</strong> - architecture-dependent floating-point coprocessor support </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./fppArchLib.html#fppSave">fppSave</a>( )</b> - save the floating-point coprocessor context<br><b><a href="./fppArchLib.html#fppRestore">fppRestore</a>( )</b> - restore the floating-point coprocessor context<br><b><a href="./fppArchLib.html#fppProbe">fppProbe</a>( )</b> - probe for the presence of a floating-point coprocessor<br><b><a href="./fppArchLib.html#fppTaskRegsGet">fppTaskRegsGet</a>( )</b> - get the floating-point registers from a task TCB<br><b><a href="./fppArchLib.html#fppTaskRegsSet">fppTaskRegsSet</a>( )</b> - set the floating-point registers of a task<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains architecture-dependent routines to support the floating-point coprocessor. The routines <b><a href="./fppArchLib.html#fppSave">fppSave</a>( )</b> and <b><a href="./fppArchLib.html#fppRestore">fppRestore</a>( )</b> saveand restore all the task floating-point context information. The routine<b><a href="./fppArchLib.html#fppProbe">fppProbe</a>( )</b> checks for the presence of the floating-point coprocessor. Theroutines <b><a href="./fppArchLib.html#fppTaskRegsSet">fppTaskRegsSet</a>( )</b> and <b><a href="./fppArchLib.html#fppTaskRegsGet">fppTaskRegsGet</a>( )</b> inspect and set coprocessorregisters on a per-task basis.<p>With the exception of <b><a href="./fppArchLib.html#fppProbe">fppProbe</a>( )</b>, the higher-level facilities in <b><a href="./dbgLib.html#top">dbgLib</a></b>and <b><a href="./usrLib.html#top">usrLib</a></b> should be used instead of these routines. For information aboutarchitecture-independent access mechanisms, see the manual entry for <b><a href="./fppLib.html#top">fppLib</a></b>.<p></blockquote><h4>INITIALIZATION</h4><blockquote><p>To activate floating-point support, <b><a href="./fppLib.html#fppInit">fppInit</a>( )</b> must be called before anytasks using the coprocessor are spawned. This is done by the root task,<b><a href="./usrConfig.html#usrRoot">usrRoot</a>( )</b>, in <b>usrConfig.c</b>. See the manual entry for <b><a href="./fppLib.html#top">fppLib</a></b>.<p></blockquote><h4>NOTE X86</h4><blockquote><p><p>There are two kind of floating-point contexts and set of routines for each kind. One is 108 bytes for older FPU (i80387, i80487, Pentium) and older MMX technology and <b><a href="./fppArchLib.html#fppSave">fppSave</a>( )</b>, <b><a href="./fppArchLib.html#fppRestore">fppRestore</a>( )</b>, <b>fppRegsToCtx( )</b>, and <b>fppCtxToRegs( )</b> are used to save and restore the context, convert to or from the <b>FPPREG_SET</b>.The other is 512 bytes for newer FPU, newer MMX technology and streaming SIMD technology (PentiumII, III, 4) and <b>fppXsave( )</b>, <b>fppXrestore( )</b>, <b>fppXregsToCtx( )</b>, and <b>fppXctxToRegs( )</b> are used to save and restore the context, convert to or from the <b>FPPREG_SET</b>. Which to use is automatically detected by checking CPUID information in <b>fppArchInit( )</b>. And <b><a href="./fppArchLib.html#fppTaskRegsSet">fppTaskRegsSet</a>( )</b> and <b><a href="./fppArchLib.html#fppTaskRegsGet">fppTaskRegsGet</a>( )</b> access the appropriate floating-point context. The bit interrogated for the automatic detection is the "Fast Save and Restore" feature flag.<p></blockquote><h4>NOTE X86 INITIALIZATION</h4><blockquote><p><p>To activate floating-point support, <b><a href="./fppLib.html#fppInit">fppInit</a>( )</b> must be called before anytasks using the coprocessor are spawned. If <b>INCLUDE_FLOATING_POINT</b> isdefined in <b>configAll.h</b>, this is done by the root task, <b><a href="./usrConfig.html#usrRoot">usrRoot</a>( )</b>, in<b>usrConfig.c</b>.<p></blockquote><h4>NOTE X86 VX FP TASK OPTION</h4><blockquote><p><p>Saving and restoring floating-point registers adds to the context switchtime of a task.Therefore, floating-point registers are <i>not</i> saved and restored for <i>every</i> task. Only those tasks spawned with the task option <b>VX_FP_TASK</b>will have floating-point state, MMX technology state, and streaming SIMD state saved and restored. <p><b>NOTE:</b> If a task does any floating-point operations, MMX operations,and streaming SIMD operation, it must be spawned with <b>VX_FP_TASK</b>.It is deadly to execute any floating-point operations in a task spawned without <b>VX_FP_TASK</b> option, and very difficult to find. To detect thatillegal/unintentional/accidental floating-point operations, a new API andmechanism is added. The mechanism is to enable or disable the FPU by toggling the TS flag in the CR0 in the new task switch hook routine -<b>fppArchSwitchHook( )</b> - respecting the <b>VX_FP_TASK</b> option. If <b>VX_FP_TASK</b>option is not set in the switching-in task, the FPU is disabled. Thusthe device-not-available exception will be raised if that task does any floating-point operations. This mechanism is disabled in the default.To enable, call the enabler - <b>fppArchSwitchHookEnable( )</b> - with a parameter TRUE(1). A parameter FALSE(0) disables the mechanism.<p></blockquote><h4>NOTE X86 MIXING MMX AND FPU INSTRUCTIONS</h4><blockquote><p><p>A task with <b>VX_FP_TASK</b> option saves and restores the FPU and MMX statewhen performing a context switch. Therefore, the application does nothave to save or restore the FPU and MMX state if the FPU and MMX instructions are not mixed within a task. Because the MMX registersare aliased to the FPU registers, care must be taken when makingtransitions between FPU instructions and MMX instructions to preventthe loss of data in the FPU and MMX registers and to prevent incoherentor unexpected result. When mixing MMX and FPU instructions within a task, follow these guidelines from Intel:<br> - Keep the code in separate modules, procedures, or routines.<br> - Do not rely on register contents across transitions between FPU<br> and MMX code modules.<br> - When transitioning between MMX code and FPU code, save the MMX<br> register state (if it will be needed in the future) and execute<br> an EMMS instruction to empty the MMX state.<br> - When transitioning between FPU and MMX code, save the FPU state,<br> if it will be needed in the future.<p></blockquote><h4>NOTE X86 MIXING SSE SSE2 FPU AND MMX INSTRUCTIONS</h4><blockquote><p><p>The XMM registers and the FPU/MMX registers represent separate execution environments, which has certain ramifications when executingSSE, SSE2, MMX and FPU instructions in the same task context:<br> - Those SSE and SSE2 instruction that operate only on the XMM <br> registers (such as the packed and scalar floating-point<br> instructions and the 128-bit SIMD integer instructions) can be<br> executed in the same instruction stream with 64-bit SIMD integer<br> or FPU instructions without any restrictions. For example, an<br> application can perform the majority of its floating-point <br> computations in the XMM registers, using the packed and scalar<br> floating-point instructions, and at the same time use the FPU<br> to perform trigonometric and other transcendental computations.<br> Likewise, an application can perform packed 64-bit and 128-bit<br> SIMD integer operations can be executed together without<br> restrictions.<br> - Those SSE and SSE2 instructions that operate on MMX registers<br> (such as the CVTPS2PI, CVTTPS2PI, CVTPI2PS, CVTPD2PI, CVTTPD2PI,<br> CVTPI2PD, MOVDQ2Q, MOVQ2DQ, PADDQ, and PSUBQ instructions) can<br> also be executed in the same instruction stream as 64-bit SIMD<br> integer or FPU instructions, however, here they subject to the<br> restrictions on the simultaneous use of MMX and FPU instructions,<br> which mentioned in the previous paragraph.<p></blockquote><h4>NOTE X86 INTERRUPT LEVEL</h4><blockquote><p><p>Floating-point registers are <i>not</i> saved and restored for interruptservice routines connected with <b><a href="./intArchLib.html#intConnect">intConnect</a>( )</b>. However, if necessary,an interrupt service routine can save and restore floating-point registersby calling routines in <b>fppALib</b>. See the manual entry for <b><a href="./intArchLib.html#intConnect">intConnect</a>( )</b> formore information.<p></blockquote><h4>NOTE X86 EXCEPTIONS</h4><blockquote><p><p>There are six FPU exceptions that can send an exception to the CPU. They are controlled by Exception Mask bits of the Control Word register. VxWorks disables them in the default configuration. They are:<br> - Precision<br> - Overflow<br> - Underflow<br> - Division by zero<br> - Denormalized operand<br> - Invalid Operation<p></blockquote><h4>NOTE ARM</h4><blockquote><p>This architecture does not currently support floating-point coprocessors.<p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>fppLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./fppLib.html#top">fppLib</a></b>, <b><a href="./intArchLib.html#intConnect">intConnect</a>( )</b>,<table><tr valign=top><td align=left><i>Motorola MC68881/882 Floating-Point Coprocessor User's Manual</i>,</tr><tr valign=top><td align=left><i>Intel 387 DX User's Manual</i>,</tr><tr valign=top><td align=left><i>Intel Architecture Software Developer's Manual</i>,</tr><tr valign=top><td align=left><i>Hitachi SH7750 Hardware Manual</i>,</tr><tr valign=top><td align=left></tr></tr></table>Gerry Kane and Joe Heinrich:<i>MIPS RISC Architecture Manual </i><hr><a name="fppSave"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>fppSave( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>fppSave( )</strong> - save the floating-point coprocessor context</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void fppSave ( FP_CONTEXT * pFpContext /* where to save context */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine saves the floating-point coprocessor context.The context saved is:<p><b>MC680x0</b>:<br> - registers <b>fpcr</b>, <b>fpsr</b>, and <b>fpiar</b><br> - registers <b>f0</b> - <b>f7</b><br> - internal state frame (if NULL, the other registers are not saved.)<p><b>MIPS</b>:<br> - register <b>fpcsr</b><br> - registers <b>fp0</b> - <b>fp31</b><p><b>SH-4</b>:<br> - registers <b>fpcsr</b> and <b>fpul</b><br> - registers <b>fr0</b> - <b>fr15</b><br> - registers <b>xf0</b> - <b>xf15</b><p><b>x86</b>:<br> 108 byte old context with fsave and frstor instruction<br> - control word, status word, tag word, <br> - instruction pointer,<br> - instruction pointer selector,<br> - last FP instruction op code,<br> - data pointer,<br> - data pointer selector,<br>⌨️ 快捷键说明
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