intarchlib.rtn

Vxworks API操作系统和驱动程序设计API。压缩的HTML文件

intLevelSet {set the interrupt level (MC680x0, x86, ARM, SimSolaris, SimNT and SH)} {<b>intLevelSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intLevelSet">intLevelSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intLock {lock out interrupts} {<b>intLock\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intLock">intLock</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intUnlock {cancel interrupt locks} {<b>intUnlock\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intUnlock">intUnlock</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intEnable {enable corresponding interrupt bits (MIPS, PowerPC, ARM)} {<b>intEnable\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intEnable">intEnable</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intDisable {disable corresponding interrupt bits (MIPS, PowerPC, ARM)} {<b>intDisable\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intDisable">intDisable</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intCRGet {read the contents of the cause register (MIPS)} {<b>intCRGet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intCRGet">intCRGet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intCRSet {write the contents of the cause register (MIPS)} {<b>intCRSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intCRSet">intCRSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intSRGet {read the contents of the status register (MIPS)} {<b>intSRGet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intSRGet">intSRGet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intSRSet {update the contents of the status register (MIPS)} {<b>intSRSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intSRSet">intSRSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intConnect {connect a C routine to a hardware interrupt} {<b>intConnect\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intConnect">intConnect</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intHandlerCreate {construct an interrupt handler for a C routine (MC680x0, x86, MIPS, SimSolaris)} {<b>intHandlerCreate\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intLockLevelSet {set the current interrupt lock-out level (MC680x0, x86, ARM, SH, SimSolaris, SimNT)} {<b>intLockLevelSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intLockLevelGet {get the current interrupt lock-out level (MC680x0, x86, ARM, SH, SimSolaris, SimNT)} {<b>intLockLevelGet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intLockLevelGet">intLockLevelGet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecBaseSet {set the vector (trap) base address (MC680x0, x86, MIPS, ARM, SimSolaris, SimNT)} {<b>intVecBaseSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecBaseGet {get the vector (trap) base address (MC680x0, x86, MIPS, ARM, SimSolaris, SimNT)} {<b>intVecBaseGet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecSet {set a CPU vector (trap) (MC680x0, x86, MIPS, SH, SimSolaris, SimNT)} {<b>intVecSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecSet">intVecSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecGet {get an interrupt vector (MC680x0, x86, MIPS, SH, SimSolaris, SimNT)} {<b>intVecGet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecGet">intVecGet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecTableWriteProtect {write-protect exception vector table (MC680x0, x86, ARM, SimSolaris, SimNT)} {<b>intVecTableWriteProtect\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecTableWriteProtect">intVecTableWriteProtect</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intUninitVecSet {set the uninitialized vector handler (ARM)} {<b>intUninitVecSet\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intUninitVecSet">intUninitVecSet</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intHandlerCreateI86 {construct an interrupt handler for a C routine (x86)} {<b>intHandlerCreateI86\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intHandlerCreateI86">intHandlerCreateI86</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecSet2 {set a CPU vector, gate type(int/trap), and selector (x86)} {<b>intVecSet2\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecSet2">intVecSet2</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intVecGet2 {get a CPU vector, gate type(int/trap), and gate selector (x86)} {<b>intVecGet2\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intVecGet2">intVecGet2</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}
intStackEnable {enable or disable the interrupt stack usage (x86)} {<b>intStackEnable\(&nbsp;\)</b>} {<b><a href="./intArchLib.html#intStackEnable">intStackEnable</a>(\&nbsp;)</b>} {VxWorks API Reference} {OS Libraries} {} {}