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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/cacheSh7622Lib.html - generated by refgen from ../sh/cacheSh7622Lib.c --> <title> cacheSh7622Lib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference : OS Libraries</i></a></p></blockquote><h1>cacheSh7622Lib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheSh7622Lib</strong> - SH7622 cache management library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./cacheSh7622Lib.html#cacheSh7622LibInit">cacheSh7622LibInit</a>( )</b> - initialize the SH7622 cache library<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains architecture-specific cache library functions forthe Hitachi SH7622 instruction and data caches. <p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>cacheLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheLib.html#top">cacheLib</a></b><p></blockquote><h4>CF </h4><blockquote><p>Writing 1 flushes all the cahe entrie (clears the U,V and LRU<br> table). Always read 0.<p></blockquote><h4>CB </h4><blockquote><p>Indicates the cache's operating mode in area P1.<br> 1 = write back mode, 0 = write through mode.<p></blockquote><h4>WT </h4><blockquote><p>Indicates the cache's operating mode in area P0,U0 and P3.<br> 1 = write through mode, 0 = write back mode.<p></blockquote><h4>CE </h4><blockquote><p>Cache enabled. <hr><a name="cacheSh7622LibInit"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>cacheSh7622LibInit( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheSh7622LibInit( )</strong> - initialize the SH7622 cache library</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS cacheSh7622LibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine initializes the cache library for the Hitachi SH7622 processor.It initializes the function pointers and configures the caches to thespecified cache modes. Modes should be set before caching is enabled.If two complementary flags are set (enable/disable), no action is takenfor any of the input flags. Data cache and istruction cache aremixed together in the SH7622.<p>Next caching modes are available for the SH7622 processor:<p><table><tr valign=top><td align=left></td><td align=left> SH7622:</td><td align=left> <b>CACHE_WRITETHROUGH</b> </td><td align=left> (cache for instruction and data)</tr><tr valign=top><td align=left></td><td align=left> </td><td align=left> <b>CACHE_COPYBACK_P1</b> </td><td align=left> (write-back cache for P1)</tr><tr valign=top><td align=left></tr></tr></table></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR if the specified caching modes were invalid.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheSh7622Lib.html#top">cacheSh7622Lib</a></b></body></html>⌨️ 快捷键说明
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