intarchlib.html

Vxworks API操作系统和驱动程序设计API。压缩的HTML文件

      add     r1,r0
      jmp     @r0             /* let intRte2 clean up stack, then rte */
      nop                     /* (delay slot) */

              .align  2
UsrIntAck:    .long   0xa0001234      /* interrupt acknowledge register */
UsrIntCnt:    .long   _usrIntCnt
IntRte2W:     .long   intRte2W
X1FFFFFFF:    .long   0x1fffffff
X80000000:    .long   0x80000000
</pre>

Note that the entire interrupt service is executed under SR.BL=1 in this
sample code.  It means that any access to virtual address space may reboot
CPU, since TLB mishit exception is blocked.  Therefore <b>usrIsr2</b> has to
access <b>usrIntCnt</b> and <b>intRte2W</b> from P1 region.  Also <b>usrIsr2</b> itself
has to be executed on P1 region, and it can be done by relocating the address
of <b>usrIsr2</b> to P1 as shown below:
<p>
<pre>IMPORT void usrIsr2 (void);

intVecSet (vector, (FUNCPTR)(((UINT32)usrIsr2 &amp; 0x1fffffff) | 0x80000000));
</pre>

In conclusion, you have to guarantee that the entire ISR does not access to
any virtual address space if you set the corresponding intPrioTable[] entry
to NULL.
<p>
</blockquote><h4>NOTE SIMNT</h4><blockquote><p>
<p>
This routine does nothing.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecGet">intVecGet</a>(&nbsp;)</b>

<hr>
<a name="intVecGet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecGet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecGet(&nbsp;)</strong> - get an interrupt vector (MC680x0, x86, MIPS, SH, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>FUNCPTR intVecGet
    (
    FUNCPTR * vector          /* vector offset */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns a pointer to the exception/interrupt handler attached
to a specified vector.  The vector is specified as an offset into the CPU's
vector table.  This vector table starts, by default, at:
<p>
<table>
<tr valign=top>
<td align=left>    MC680x0:     </td><td align=left> 0</tr>
<tr valign=top>
<td align=left>    MIPS:        </td><td align=left> <b>excBsrTbl</b> in <b><a href="./excArchLib.html#top">excArchLib</a></b></tr>
<tr valign=top>
<td align=left>    x86:         </td><td align=left> 0</tr>
<tr valign=top>
<td align=left>    SH702x/SH703x/SH704x/SH76xx: </td><td align=left> <b>excBsrTbl</b> in <b><a href="./excArchLib.html#top">excArchLib</a></b></tr>
<tr valign=top>
<td align=left>    SH77xx:      </td><td align=left> vbr + 0x800</tr>
<tr valign=top>
<td align=left>    SimSolaris:  </td><td align=left> 0</tr>
<tr valign=top>
<td align=left></tr>
</tr>

</table>

However, the vector table may be set to start at any address with
<b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b> (on CPUs for which it is available).
<p>
This routine takes an interrupt vector as a parameter, which is the byte
offset into the vector table. Macros are provided to convert between interrupt
vectors and interrupt numbers, see <b><a href="./intArchLib.html#top">intArchLib</a></b>.
<p>
</blockquote><h4>NOTE SIMNT</h4><blockquote><p>
<p>
This routine does nothing and always returns 0.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
<p>
A pointer to the exception/interrupt handler attached to the specified vector.
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>

<hr>
<a name="intVecTableWriteProtect"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecTableWriteProtect(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecTableWriteProtect(&nbsp;)</strong> - write-protect exception vector table (MC680x0, x86, ARM, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS intVecTableWriteProtect (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
If the unbundled Memory Management Unit (MMU) support package (VxVMI) is
present, this routine write-protects the exception vector table to
protect it from being accidentally corrupted.
<p>
Note that other data structures contained in the page will also be 
write-protected.  In the default VxWorks configuration, the exception vector
table is located at location 0 in memory.  Write-protecting this affects
the backplane anchor, boot configuration information, and potentially the
text segment (assuming the default text location of 0x1000.)  All code
that manipulates these structures has been modified to write-enable 
memory for the duration of the operation.  If you select a different
address for the exception vector table, be sure it resides in a page
separate from other writable data structures.
<p>
</blockquote><h4>NOTE SIMSOLARIS, SIMNT</h4><blockquote><p>
<p>
This routine always returns ERROR on simulators.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if memory cannot be write-protected.
<p>
</blockquote><h4>ERRNO</h4><blockquote><p>
<b>S_intLib_VEC_TABLE_WP_UNAVAILABLE</b>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intUninitVecSet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intUninitVecSet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intUninitVecSet(&nbsp;)</strong> - set the uninitialized vector handler (ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intUninitVecSet
    (
    VOIDFUNCPTR routine       /* ptr to user routine */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine installs a handler for the uninitialized vectors to be
called when any uninitialised vector is entered.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intHandlerCreateI86"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intHandlerCreateI86(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intHandlerCreateI86(&nbsp;)</strong> - construct an interrupt handler for a C routine (x86)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>FUNCPTR intHandlerCreateI86
    (
    FUNCPTR routine,          /* routine to be called */
    int     parameter,        /* parameter to be passed to routine */
    FUNCPTR routineBoi,       /* BOI routine to be called */
    int     parameterBoi,     /* parameter to be passed to routineBoi */
    FUNCPTR routineEoi,       /* EOI routine to be called */
    int     parameterEoi      /* parameter to be passed to routineEoi */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine builds an interrupt handler around a specified C routine.
This interrupt handler is then suitable for connecting to a specific
vector address with <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>.  The interrupt handler is invoked in
supervisor mode at interrupt level.  A proper C environment is
established, the necessary registers saved, and the stack set up.
<p>
The routine can be any normal C code, except that it must not invoke
certain operating system functions that may block or perform I/O
operations.
<p>
</blockquote><h4>IMPLEMENTATION</h4><blockquote><p>
<p>
This routine builds an interrupt handler of the following form in
allocated memory:
<p>
<pre>00  e8 kk kk kk kk            call    _intEnt         * tell kernel
05  50                        pushl   %eax            * save regs
06  52                        pushl   %edx
07  51                        pushl   %ecx
08  68 pp pp pp pp            pushl   $_parameterBoi  * push BOI param
13  e8 rr rr rr rr            call    _routineBoi     * call BOI routine
18  68 pp pp pp pp            pushl   $_parameter     * push param
23  e8 rr rr rr rr            call    _routine        * call C routine
28  68 pp pp pp pp            pushl   $_parameterEoi  * push EOI param
33  e8 rr rr rr rr            call    _routineEoi     * call EOI routine
38  83 c4 0c                  addl    $12, %esp       * pop param
41  59                        popl    %ecx            * restore regs
42  5a                        popl    %edx
43  58                        popl    %eax
44  e9 kk kk kk kk            jmp     _intExit        * exit via kernel
</pre>

Third and fourth parameter of <b><a href="./intArchLib.html#intHandlerCreateI86">intHandlerCreateI86</a>(&nbsp;)</b> are the BOI routine 
address and its parameter that are inserted into the code as "routineBoi" 
and "parameterBoi". 
Fifth and sixth parameter of <b><a href="./intArchLib.html#intHandlerCreateI86">intHandlerCreateI86</a>(&nbsp;)</b> are the EOI routine 
address and its parameter that are inserted into the code as "routineEoi" 
and "parameterEoi". 
The BOI routine detects if this interrupt is stray/spurious/phantom by
interrogating the interrupt controller, and returns from the interrupt
if it is.  The EOI routine issues End Of Interrupt signal to the 
interrupt controller, if it is required by the controller.  
Each interrupt controller has its own BOI and EOI routine.  They are
located in the BSP, and their address and parameter are taken by the
intEoiGet function (set to <b>sysIntEoiGet(&nbsp;)</b> in the BSP).
The Tornado 2, and later, BSPs should use the BOI and EOI mechanism with
intEoiGet function pointer.
<p>
To keep the Tornado 101 BSP backward compatible, the function pointer 
intEOI is not removed.  If intEoiGet is NULL, it should be set to the
<b>sysIntEoiGet(&nbsp;)</b> routine in the BSP, <b><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a>(&nbsp;)</b> and the intEOI 
function pointer (set to <b>sysIntEOI(&nbsp;)</b> in the Tornado 101 BSP) is used.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
A pointer to the new interrupt handler, or NULL if memory
is insufficient.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intVecSet2"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecSet2(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecSet2(&nbsp;)</strong> - set a CPU vector, gate type(int/trap), and selector (x86)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intVecSet2
    (
    FUNCPTR * vector,         /* vector offset */
    FUNCPTR   function,       /* address to place in vector */
    int       idtGate,        /* IDT_TRAP_GATE or IDT_INT_GATE */
    int       idtSelector     /* sysCsExc or sysCsInt */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine attaches an exception handler to a specified vector,
with the type of the gate and the selector of the gate.  
The vector is specified as an offset into the CPU's vector table.  This
vector table starts, by default, at address 0.  
However, the vector table may be set to start at any address with
<b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>.  The vector table is set up in <b><a href="./usrConfig.html#usrInit">usrInit</a>(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecGet">intVecGet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecGet2">intVecGet2</a>(&nbsp;)</b>

<hr>
<a name="intVecGet2"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecGet2(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecGet2(&nbsp;)</strong> - get a CPU vector, gate type(int/trap), and gate selector (x86)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intVecGet2
    (
    FUNCPTR * vector,         /* vector offset */
    FUNCPTR * pFunction,      /* address to place in vector */
    int *     pIdtGate,       /* IDT_TRAP_GATE or IDT_INT_GATE */
    int *     pIdtSelector    /* sysCsExc or sysCsInt */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine gets a pointer to the exception/interrupt handler attached
to a specified vector, the type of the gate, the selector of the gate.  
The vector is specified as an offset into the CPU's vector table.  
This vector table starts, by default, at address 0.
However, the vector table may be set to start at any address with
<b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecGet">intVecGet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecSet2">intVecSet2</a>(&nbsp;)</b>

<hr>
<a name="intStackEnable"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intStackEnable(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intStackEnable(&nbsp;)</strong> - enable or disable the interrupt stack usage (x86)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS intStackEnable
    (
    BOOL enable               /* TRUE to enable, FALSE to disable */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine enables or disables the interrupt stack usage and is only 
callable from the task level. An Error is returned for any other calling 
context. The interrupt stack usage is disabled in the default configuration
for the backward compatibility.  Routines that manipulate the interrupt
stack, are located in the file <b>i86/windALib.s</b>. These routines include
<b><a href="./intArchLib.html#intStackEnable">intStackEnable</a>(&nbsp;)</b>, <b>intEnt(&nbsp;)</b> and <b>intExit(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if it is not in the task level.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

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