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Vxworks API操作系统和驱动程序设计API。压缩的HTML文件

</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
On the ARM, this call establishes the interrupt level to be set when
<b><a href="./intArchLib.html#intLock">intLock</a>(&nbsp;)</b> is called.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intLockLevelGet">intLockLevelGet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intLock">intLock</a>(&nbsp;)</b>, <b><a href="./taskLib.html#taskLock">taskLock</a>(&nbsp;)</b>

<hr>
<a name="intLockLevelGet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intLockLevelGet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intLockLevelGet(&nbsp;)</strong> - get the current interrupt lock-out level (MC680x0, x86, ARM, SH, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>int intLockLevelGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns the current interrupt lock-out level, which is
set by <b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>(&nbsp;)</b> and stored in the globally accessible
variable <b>intLockMask</b>.  This is the interrupt level currently
masked when interrupts are locked out by <b><a href="./intArchLib.html#intLock">intLock</a>(&nbsp;)</b>.  The default
lock-out level (MC680x0 = 7, x86 = 1, SH = 15)
is initially set by <b><a href="./kernelLib.html#kernelInit">kernelInit</a>(&nbsp;)</b> when VxWorks is initialized.
<p>
</blockquote><h4>NOTE SIMNT</h4><blockquote><p>
<p>
This routine does nothing.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The interrupt level currently stored in the interrupt
lock-out mask. (ARM = ERROR always)
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>(&nbsp;)</b>

<hr>
<a name="intVecBaseSet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecBaseSet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecBaseSet(&nbsp;)</strong> - set the vector (trap) base address (MC680x0, x86, MIPS, ARM, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intVecBaseSet
    (
    FUNCPTR * baseAddr        /* new vector (trap) base address */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine sets the vector (trap) base address.  The CPU's vector base
register is set to the specified value, and subsequent calls to <b><a href="./intArchLib.html#intVecGet">intVecGet</a>(&nbsp;)</b>
or <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b> will use this base address.  The vector base address is
initially 0, until modified by calls to this routine.
<p>
</blockquote><h4>NOTE 68000</h4><blockquote><p>
<p>
The 68000 has no vector base register; thus, this routine is a no-op for
68000 systems.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
The MIPS processors have no vector base register;
thus this routine is a no-op for this architecture.
<p>
</blockquote><h4>NOTE SH77XX</h4><blockquote><p>
<p>
This routine sets <i>baseAddr</i> to vbr, then loads an interrupt dispatch
code to (vbr + 0x600).  When SH77XX processor accepts an interrupt request,
it sets an exception code to INTEVT register and jumps to (vbr + 0x600).
Thus this dispatch code is commonly used for all interrupts' handling.
<p>
The exception codes are 12bits width, and interleaved by 0x20.  VxWorks
for SH77XX locates a vector table at (vbr + 0x800), and defines the vector
offsets as (exception codes / 8).  This vector table is commonly used by
all interrupts, exceptions, and software traps.
<p>
All SH77XX processors have INTEVT register at address 0xffffffd8.  The SH7707
processor has yet another INTEVT2 register at address 0x04000000, to identify
its enhanced interrupt sources.  The dispatch code obtains the address
of INTEVT register from a global constant <b>intEvtAdrs</b>.  The constant is
defined in <b><a href="./sysLib.html#top">sysLib</a></b>, thus the selection of INTEVT/INTEVT2 is configurable
at BSP level.  The <b>intEvtAdrs</b> is loaded to (vbr + 4) by <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>.
<p>
After fetching the exception code, the interrupt dispatch code applies
a new interrupt mask to the status register, and jumps to an individual
interrupt handler.  The new interrupt mask is taken from <b>intPrioTable[]</b>,
which is defined in <b>sysALib</b>.  The <b>intPrioTable[]</b> is loaded to
(vbr + 0xc00) by <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>.
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
The ARM processors have no vector base register;
thus this routine is a no-op for this architecture.
<p>
</blockquote><h4>NOTE SIMSOLARIS, SIMNT</h4><blockquote><p>
<p>
This routine does nothing.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecGet">intVecGet</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>

<hr>
<a name="intVecBaseGet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecBaseGet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecBaseGet(&nbsp;)</strong> - get the vector (trap) base address (MC680x0, x86, MIPS, ARM, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>FUNCPTR *intVecBaseGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns the current vector base address, which is set
with <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The current vector base address
(MIPS = 0 always, ARM = 0 always, SimSolaris = 0 always and 
SimNT = 0 always).
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b>

<hr>
<a name="intVecSet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intVecSet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intVecSet(&nbsp;)</strong> - set a CPU vector (trap) (MC680x0, x86, MIPS, SH, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intVecSet
    (
    FUNCPTR * vector,         /* vector offset */
    FUNCPTR   function        /* address to place in vector */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine attaches an exception/interrupt/trap handler to a specified 
vector.  The vector is specified as an offset into the CPU's vector table. 
This vector table starts, by default, at:
<p>
<table>
<tr valign=top>
<td align=left>    MC680x0:     </td><td align=left> 0</tr>
<tr valign=top>
<td align=left>    MIPS:        </td><td align=left> <b>excBsrTbl</b> in <b><a href="./excArchLib.html#top">excArchLib</a></b></tr>
<tr valign=top>
<td align=left>    x86:         </td><td align=left> 0</tr>
<tr valign=top>
<td align=left>    SH702x/SH703x/SH704x/SH76xx: </td><td align=left> <b>excBsrTbl</b> in <b><a href="./excArchLib.html#top">excArchLib</a></b></tr>
<tr valign=top>
<td align=left>    SH77xx:      </td><td align=left> vbr + 0x800</tr>
<tr valign=top>
<td align=left>    SimSolaris:  </td><td align=left> 0</tr>
<tr valign=top>
<td align=left></tr>
</tr>

</table>

However, the vector table may be set to start at any address with
<b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>(&nbsp;)</b> (on CPUs for which it is available).  The vector table is
set up in <b><a href="./usrConfig.html#usrInit">usrInit</a>(&nbsp;)</b>.
<p>
This routine takes an interrupt vector as a parameter, which is the byte
offset into the vector table. Macros are provided to convert between interrupt
vectors and interrupt numbers, see <b><a href="./intArchLib.html#top">intArchLib</a></b>.
<p>
The <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b> routine puts this generated code into the trap table
entry corresponding to <i>vector</i>.
<p>
Window overflow and window underflow are sacred to
the kernel and may not be pre-empted.  They are written here
only to track changing trap base registers (TBRs).
With the "branch anywhere" scheme (as opposed to the branch PC-relative
+/-8 megabytes) the first instruction in the vector table must not be a 
change of flow control nor affect any critical registers.  The JMPL that 
replaces the BA will always execute the next vector's first instruction.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
On MIPS CPUs the vector table is set up statically in software.
<p>
</blockquote><h4>NOTE SH77XX</h4><blockquote><p>
<p>
The specified interrupt handler <i>function</i> has to coordinate with an interrupt
stack frame which is specially designed for SH77XX version of VxWorks:
<p>
<pre>   [ task's stack ]       [ interrupt stack ]

      |  xxx  | high address
      |  yyy  |               +-------+
      |__zzz__|&lt;--------------|task'sp|  0
      |       |               |INTEVT | -4
      |       | low address   |  ssr  | -8
                              |_ spc _| -12 &lt;- sp (non-nested interrupt)
                              :       :
                              :       :
                              :_______:
                              |INTEVT |  0
                              |  ssr  | -4
                              |_ spc _| -8  &lt;- sp (nested interrupt)
                              |       |
</pre>

This interrupt stack frame is formed by a common interrupt dispatch code
which is loaded at (vbr + 0x600).  You usually do not have to pay any
attention to this stack frame, since <b><a href="./intArchLib.html#intConnect">intConnect</a>(&nbsp;)</b> automatically appends
an appropriate stack manipulation code to your interrupt service routine.
The <b><a href="./intArchLib.html#intConnect">intConnect</a>(&nbsp;)</b> assumes that your interrupt service routine (ISR) is
written in C, thus it also wraps your ISR in minimal register save/restore
codes.  However if you need a very fast response time to a particular
interrupt request, you might want to skip this register save/restore
sequence by directly attaching your ISR to the corresponding vector table
entry using <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>.  Note that this technique is only applicable to
an interrupt service with NO VxWorks system call.  For example it is not
allowed to use <b><a href="./semLib.html#semGive">semGive</a>(&nbsp;)</b> or <b><a href="./logLib.html#logMsg">logMsg</a>(&nbsp;)</b> in the interrupt service routine which
is directly attached to vector table by <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>.  To facilitate the
direct usage of <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b> by user, a special entry point to exit an
interrupt context is provided within the SH77XX version of VxWorks kernel.
This entry point is located at address (vbr + intRte1W), here the intRte1W
is a global symbol for the vbr offset of the entry point in 16 bit length.
This entry point <b>intRte1</b> assumes that the current register bank is 0
(SR.RB == 0), and r1 and r0 are still saved on the interrupt stack, and
it also requires 0x70000000 in r0. Then <b>intRte1</b> properly cleans up the
interrupt stack and executes <i>rte</i> instruction to return to the previous
interrupt or task context.  The following code is an example of <b>intRte1</b>
usage.  Here the corresponding intPrioTable[] entry is assumed to be
0x400000X0, namely MD=1, RB=0, BL=0 at the beginning of <b>usrIsr1</b>.
<p>
<pre>      .text
      .align  2
      .global _usrIsr1
      .type   _usrIsr1,@function
      .extern _usrRtn
      .extern intRte1W
                              /* intPrioTable[] sets SR to 0x400000X0 */
_usrIsr1:
      mov.l   r0,@-sp         /* must save r0 first (BANK0) */
      mov.l   r1,@-sp         /* must save r1 second (BANK0) */

      mov.l   r2,@-sp         /* save rest of volatile registers (BANK0) */
      mov.l   r3,@-sp
      mov.l   r4,@-sp
      mov.l   r5,@-sp
      mov.l   r6,@-sp
      mov.l   r7,@-sp
      sts.l   pr,@-sp
      sts.l   mach,@-sp
      sts.l   macl,@-sp

      mov.l   UsrRtn,r0
      jsr     @r0             /* call user's C routine */
      nop                     /* (delay slot) */

      lds.l   @sp+,macl       /* restore volatile registers (BANK0) */
      lds.l   @sp+,mach
      lds.l   @sp+,pr
      mov.l   @sp+,r7
      mov.l   @sp+,r6
      mov.l   @sp+,r5
      mov.l   @sp+,r4
      mov.l   @sp+,r3
      mov.l   @sp+,r2
                              /* intRte1 restores r1 and r0 */
      mov.l   IntRte1W,r1
      mov.w   @r1,r0
      stc     vbr,r1
      add     r0,r1
      mov.l   IntRteSR,r0     /* r0: 0x70000000 */
      jmp     @r1             /* let intRte1 clean up stack, then rte */
      nop                     /* (delay slot) */

              .align  2
UsrRtn:       .long   _usrRtn         /* user's C routine */
IntRteSR:     .long   0x70000000      /* MD=1, RB=1, BL=1 */
IntRte1W:     .long   intRte1W
</pre>

The <b>intRte1</b> sets r0 to status register (SR: 0x70000000), to safely restore
SPC/SSR and to clean up the interrupt stack.  Note that TLB mishit exception
immediately reboots CPU while SR.BL=1.  To avoid this fatal condition, VxWorks
loads the <b>intRte1</b> code and the interrupt stack to a physical address space
(P1) where no TLB mishit happens.
<p>
Furthermore, there is another special entry point called <b>intRte2</b> at an
address (vbr + intRte2W).  The <b>intRte2</b> assumes that SR is already set to
0x70000000 (MD: 1, RB: 1, BL: 1), then it does not restore r1 and r0.
While SR value is 0x70000000, you may use r0,r1,r2,r3 in BANK1 as volatile
registers.  The rest of BANK1 registers (r4,r5,r6,r7) are non-volatile, so
if you need to use them then you have to preserve their original values by
saving/restoring them on the interrupt stack.  So, if you need the ultimate
interrupt response time, you may set the corresponding intPrioTable[] entry
to NULL and manage your interrupt service only with r0,r1,r2,r3 in BANK1
as shown in the next sample code:
<p>
<pre>      .text
      .global  _usrIsr2
      .type    _usrIsr2,@function
      .extern  _usrIntCnt     /* interrupt counter */
      .extern  intRte2W
      .align   2
                              /* MD=1, RB=1, BL=1, since SR is not */
                              /* substituted from intPrioTable[].  */
_usrIsr2:
      mov.l   UsrIntAck,r1
      mov     #0x1,r0
      mov.b   r0,@r1          /* acknowledge interrupt */

      mov.l   UsrIntCnt,r1
      mov.l   X1FFFFFFF,r2
      mov.l   X80000000,r3
      and     r2,r1
      or      r3,r1           /* r1: _usrIntCnt address in P1 */
      mov.l   @r1,r0
      add     #1,r0
      mov.l   r0,@r1          /* increment counter */

      mov.l   IntRte2W,r1
      and     r2,r1
      or      r3,r1           /* r1: intRte2W address in P1 */
      mov.w   @r1,r0
      stc     vbr,r1