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Vxworks API操作系统和驱动程序设计API。压缩的HTML文件

    int level                 /* new interrupt bits (0x0 - 0xff00) */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
On MIPS and PowerPC architectures, this routine disables the corresponding
interrupt bits from the present status register.  
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
ARM processors generally do not have on-chip interrupt controllers.
Control of interrupts is a BSP-specific matter. This routine calls a
BSP-specific routine to disable a particular interrupt level,
regardless of the current interrupt mask level.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
For MIPS, the macros <b>SR_IBIT1</b> - <b>SR_IBIT8</b> define bits that may be set.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK or ERROR. (MIPS: The previous contents of the status register).
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intCRGet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intCRGet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intCRGet(&nbsp;)</strong> - read the contents of the cause register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>int intCRGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine reads and returns the contents of the MIPS cause
register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The contents of the cause register.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intCRSet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intCRSet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intCRSet(&nbsp;)</strong> - write the contents of the cause register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intCRSet
    (
    int value                 /* value to write to cause register */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine writes the contents of the MIPS cause register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intSRGet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intSRGet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intSRGet(&nbsp;)</strong> - read the contents of the status register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>int intSRGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine reads and returns the contents of the MIPS status
register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The previous contents of the status register.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intSRSet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intSRSet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intSRSet(&nbsp;)</strong> - update the contents of the status register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>int intSRSet
    (
    int value                 /* value to write to status register */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine updates and returns the previous contents of the MIPS
status register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The previous contents of the status register.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intConnect"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intConnect(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intConnect(&nbsp;)</strong> - connect a C routine to a hardware interrupt</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS intConnect
    (
    VOIDFUNCPTR * vector,     /* interrupt vector to attach to */
    VOIDFUNCPTR   routine,    /* routine to be called */
    int           parameter   /* parameter to be passed to routine */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine connects a specified C routine to a specified interrupt
vector.  The address of <i>routine</i> is generally stored at <i>vector</i> so
that <i>routine</i> is called with <i>parameter</i> when the interrupt occurs.
The routine is invoked in supervisor mode at interrupt level.  A proper
C environment is established, the necessary registers saved, and the
stack set up.
<p>
The routine can be any normal C code, except that it must not invoke
certain operating system functions that may block or perform I/O
operations.
<p>
This routine generally simply calls <b><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a>(&nbsp;)</b> and
<b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>.  The address of the handler returned by <b><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a>(&nbsp;)</b>
is what actually goes in the interrupt vector.
<p>
This routine takes an interrupt vector as a parameter, which is the byte
offset into the vector table. Macros are provided to convert between interrupt
vectors and interrupt numbers, see <b><a href="./intArchLib.html#top">intArchLib</a></b>.
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
ARM processors generally do not have on-chip interrupt controllers.
Control of interrupts is a BSP-specific matter. This routine calls a
BSP-specific routine to install the handler such that, when the
interrupt occurs, <i>routine</i> is called with <i>parameter</i>.
<p>
</blockquote><h4>NOTE X86</h4><blockquote><p>
<p>
Refer to the special x86 routine <b><a href="./intArchLib.html#intHandlerCreateI86">intHandlerCreateI86</a>(&nbsp;)</b>.
<p>
</blockquote><h4>NOTE SH</h4><blockquote><p>
<p>
The on-chip interrupt controller (INTC) design of SH architecture depends
on the processor type, but there are some similarities.  The number of
external interrupt inputs are limited, so it may necessary to multiplex
some interrupt requests.  However most of them are auto-vectored, thus have
only one vector to an external interrupt input.  As a framework to handle
this type of multiplexed interrupt, you can use your original intConnect
code by hooking it to <b>_func_intConnectHook</b> pointer.  If <b>_func_intConnectHook</b>
is set, the SH version of <b><a href="./intArchLib.html#intConnect">intConnect</a>(&nbsp;)</b> simply calls the hooked routine with
same arguments, then returns the status of hooked routine.  A <b><a href="./sysLib.html#top">sysLib</a></b> sample
is shown below:
<p>
<pre>#include "intLib.h"
#include "iv.h"               /* INUM_INTR_HIGH for SH7750/SH7700 */

#define SYS_INT_TBL_SIZE      (255 - INUM_INTR_HIGH)

typedef struct
    {
    VOIDFUNCPTR routine;      /* routine to be called */
    int         parameter;    /* parameter to be passed */
    } SYS_INT_TBL;

LOCAL SYS_INT_TBL sysIntTbl [SYS_INT_TBL_SIZE]; /* local vector table */

LOCAL int sysInumVirtBase = INUM_INTR_HIGH + 1;

STATUS sysIntConnect
    (
    VOIDFUNCPTR *vec,         /* interrupt vector to attach to     */
    VOIDFUNCPTR routine,      /* routine to be called              */
    int         param         /* parameter to be passed to routine */
    )
    {
    FUNCPTR intDrvRtn;
 
    if (vec &gt;= INUM_TO_IVEC (0) &amp;&amp; vec &lt; INUM_TO_IVEC (sysInumVirtBase))
        {
        /* do regular intConnect() process */

        intDrvRtn = intHandlerCreate ((FUNCPTR)routine, param);
 
        if (intDrvRtn == NULL)
            return ERROR;
 
        /* make vector point to synthesized code */
 
        intVecSet ((FUNCPTR *)vec, (FUNCPTR)intDrvRtn);
        }
    else
        {
        int index = IVEC_TO_INUM (vec) - sysInumVirtBase;
 
        if (index &lt; 0 || index &gt;= SYS_INT_TBL_SIZE)
            return ERROR;
 
        sysIntTbl [index].routine   = routine;
        sysIntTbl [index].parameter = param;
        }
 
    return OK;
    }

void sysHwInit (void)
    {
    ...
    _func_intConnectHook = (FUNCPTR)sysIntConnect;
    }

LOCAL void sysVmeIntr (void)
    {
    volatile UINT32 vec = *VME_VEC_REGISTER;  /* get VME interrupt vector */
    int i = vec - sysInumVirtBase;
 
    if (i &gt;= 0 &amp;&amp; i &lt; SYS_INT_TBL_SIZE &amp;&amp; sysIntTbl[i].routine != NULL)
        (*sysIntTbl[i].routine)(sysIntTbl[i].parameter);
    else
        logMsg ("uninitialized VME interrupt: vec = %d\n", vec,0,0,0,0,0);
    }

void sysHwInit2 (void)
    {
    int i;
    ...
    /* initialize VME interrupts dispatch table */

    for (i = 0; i &lt; SYS_INT_TBL_SIZE; i++)
        {
        sysIntTbl[i].routine   = (VOIDFUNCPTR)NULL;
        sysIntTbl[i].parameter = NULL;
        }

    /* connect generic VME interrupts handler */

    intConnect (INT_VEC_VME, sysVmeIntr, NULL);
    ...
    }
</pre>

The used vector numbers of SH processors are limited to certain ranges,
depending on the processor type. The <b>sysInumVirtBase</b> should be initialized
to a value higher than the last used vector number, defined as <b>INUM_INTR_HIGH</b>.
It is typically safe to set <b>sysInumVirtBase</b> to (<b>INUM_INTR_HIGH</b> + 1).
<p>
The <b><a href="../bsp/rbtx4927_mips32sf/sysLib.html#sysIntConnect" >sysIntConnect</a>(&nbsp;)</b> routine simply acts as the regular <b><a href="./intArchLib.html#intConnect">intConnect</a>(&nbsp;)</b> if 
<i>vector</i> is smaller than <b>INUM_TO_IVEC</b> (sysInumVirtBase), so <b><a href="../bsp/ads8260/sysLib.html#sysHwInit2" >sysHwInit2</a>(&nbsp;)</b> 
connects a common VME interrupt dispatcher <b>sysVmeIntr</b> to the multiplexed
interrupt vector. If <i>vector</i> is equal to or greater than <b>INUM_TO_IVEC</b> 
(sysInumVirtBase), the <b><a href="../bsp/rbtx4927_mips32sf/sysLib.html#sysIntConnect" >sysIntConnect</a>(&nbsp;)</b> fills a local vector entry in 
sysIntTbl[] with an individual VME interrupt handler, in a coordinated 
manner with <b>sysVmeIntr</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the interrupt handler cannot be built.
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a>(&nbsp;)</b>, <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>

<hr>
<a name="intHandlerCreate"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intHandlerCreate(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intHandlerCreate(&nbsp;)</strong> - construct an interrupt handler for a C routine (MC680x0, x86, MIPS, SimSolaris)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>FUNCPTR intHandlerCreate
    (
    FUNCPTR routine,          /* routine to be called */
    int     parameter         /* parameter to be passed to routine */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine builds an interrupt handler around the specified C routine.
This interrupt handler is then suitable for connecting to a specific
vector address with <b><a href="./intArchLib.html#intVecSet">intVecSet</a>(&nbsp;)</b>.  The interrupt handler is invoked in
supervisor mode at interrupt level.  A proper C environment is
established, the necessary registers saved, and the stack set up.
<p>
The routine can be any normal C code, except that it must not invoke
certain operating system functions that may block or perform I/O
operations.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
A pointer to the new interrupt handler, or NULL if memory 
is insufficient.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intLockLevelSet"></a>
<p align=right>
<a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p>

</blockquote><h1>intLockLevelSet(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong>intLockLevelSet(&nbsp;)</strong> - set the current interrupt lock-out level (MC680x0, x86, ARM, SH, SimSolaris, SimNT)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intLockLevelSet
    (
    int newLevel              /* new interrupt level */
    )
</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine sets the current interrupt lock-out level and stores it
in the globally accessible variable <b>intLockMask</b>.  The specified
interrupt level is masked when interrupts are locked by
<b><a href="./intArchLib.html#intLock">intLock</a>(&nbsp;)</b>.  The default lock-out level (MC680x0 = 7,
x86 = 1, SH = 15) is initially set by <b><a href="./kernelLib.html#kernelInit">kernelInit</a>(&nbsp;)</b> when
VxWorks is initialized.
<p>
</blockquote><h4>NOTE SIMSOLARIS, SIMNT</h4><blockquote><p>
<p>
This routine does nothing.
<p>