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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/intArchLib.html - generated by refgen from intArchLib.c --> <title> intArchLib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference : OS Libraries</i></a></p></blockquote><h1>intArchLib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>intArchLib</strong> - architecture-dependent interrupt library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./intArchLib.html#intLevelSet">intLevelSet</a>( )</b> - set the interrupt level (MC680x0, x86, ARM, SimSolaris, SimNT and SH)<br><b><a href="./intArchLib.html#intLock">intLock</a>( )</b> - lock out interrupts<br><b><a href="./intArchLib.html#intUnlock">intUnlock</a>( )</b> - cancel interrupt locks<br><b><a href="./intArchLib.html#intEnable">intEnable</a>( )</b> - enable corresponding interrupt bits (MIPS, PowerPC, ARM)<br><b><a href="./intArchLib.html#intDisable">intDisable</a>( )</b> - disable corresponding interrupt bits (MIPS, PowerPC, ARM)<br><b><a href="./intArchLib.html#intCRGet">intCRGet</a>( )</b> - read the contents of the cause register (MIPS)<br><b><a href="./intArchLib.html#intCRSet">intCRSet</a>( )</b> - write the contents of the cause register (MIPS)<br><b><a href="./intArchLib.html#intSRGet">intSRGet</a>( )</b> - read the contents of the status register (MIPS)<br><b><a href="./intArchLib.html#intSRSet">intSRSet</a>( )</b> - update the contents of the status register (MIPS)<br><b><a href="./intArchLib.html#intConnect">intConnect</a>( )</b> - connect a C routine to a hardware interrupt<br><b><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a>( )</b> - construct an interrupt handler for a C routine (MC680x0, x86, MIPS, SimSolaris)<br><b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>( )</b> - set the current interrupt lock-out level (MC680x0, x86, ARM, SH, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intLockLevelGet">intLockLevelGet</a>( )</b> - get the current interrupt lock-out level (MC680x0, x86, ARM, SH, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>( )</b> - set the vector (trap) base address (MC680x0, x86, MIPS, ARM, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a>( )</b> - get the vector (trap) base address (MC680x0, x86, MIPS, ARM, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intVecSet">intVecSet</a>( )</b> - set a CPU vector (trap) (MC680x0, x86, MIPS, SH, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intVecGet">intVecGet</a>( )</b> - get an interrupt vector (MC680x0, x86, MIPS, SH, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intVecTableWriteProtect">intVecTableWriteProtect</a>( )</b> - write-protect exception vector table (MC680x0, x86, ARM, SimSolaris, SimNT)<br><b><a href="./intArchLib.html#intUninitVecSet">intUninitVecSet</a>( )</b> - set the uninitialized vector handler (ARM)<br><b><a href="./intArchLib.html#intHandlerCreateI86">intHandlerCreateI86</a>( )</b> - construct an interrupt handler for a C routine (x86)<br><b><a href="./intArchLib.html#intVecSet2">intVecSet2</a>( )</b> - set a CPU vector, gate type(int/trap), and selector (x86)<br><b><a href="./intArchLib.html#intVecGet2">intVecGet2</a>( )</b> - get a CPU vector, gate type(int/trap), and gate selector (x86)<br><b><a href="./intArchLib.html#intStackEnable">intStackEnable</a>( )</b> - enable or disable the interrupt stack usage (x86)<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library provides architecture-dependent routines to manipulateand connect to hardware interrupts. Any C language routine can beconnected to any interrupt by calling <b><a href="./intArchLib.html#intConnect">intConnect</a>( )</b>. Vectors can beaccessed directly by <b><a href="./intArchLib.html#intVecSet">intVecSet</a>( )</b> and <b><a href="./intArchLib.html#intVecGet">intVecGet</a>( )</b>. The vector (trap)base register (if present) can be accessed by the routines<b><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a>( )</b> and <b><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a>( )</b>.<p>Tasks can lock and unlock interrupts by calling <b><a href="./intArchLib.html#intLock">intLock</a>( )</b> and <b><a href="./intArchLib.html#intUnlock">intUnlock</a>( )</b>.The lock-out level can be set and reported by <b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>( )</b> and<b><a href="./intArchLib.html#intLockLevelGet">intLockLevelGet</a>( )</b> (MC680x0, x86, ARM and SH only).The routine <b><a href="./intArchLib.html#intLevelSet">intLevelSet</a>( )</b> changes the current interrupt level of theprocessor (MC680x0, ARM, SimSolaris and SH).<p></blockquote><h4>WARNING</h4><blockquote><p>Do not call VxWorks system routines with interrupts locked.Violating this rule may re-enable interrupts unpredictably.<p></blockquote><h4>INTERRUPT VECTORS AND NUMBERS</h4><blockquote><p>Most of the routines in this library take an interrupt vector as aparameter, which is generally the byte offset into the vector table.Macros are provided to convert between interrupt vectors and interruptnumbers:<dl><dt><b>IVEC_TO_INUM</b>(intVector)<dd>converts a vector to a number.<dt><b>INUM_TO_IVEC</b>(intNumber)<dd>converts a number to a vector.<dt><b>TRAPNUM_TO_IVEC</b>(trapNumber)<dd>converts a trap number to a vector.<br> </dl></blockquote><h4>EXAMPLE</h4><blockquote><p><p>To switch between one of several routines for a particular interrupt,the following code fragment is one alternative:<pre> vector = INUM_TO_IVEC(some_int_vec_num); oldfunc = intVecGet (vector); newfunc = intHandlerCreate (routine, parameter); intVecSet (vector, newfunc); ... intVecSet (vector, oldfunc); /* use original routine */ ... intVecSet (vector, newfunc); /* reconnect new routine */</pre></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>iv.h</b>, <b>intLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./intLib.html#top">intLib</a></b><hr><a name="intLevelSet"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>intLevelSet( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>intLevelSet( )</strong> - set the interrupt level (MC680x0, x86, ARM, SimSolaris, SimNT and SH)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>int intLevelSet ( int level /* new interrupt level mask */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine changes the interrupt mask in the status register to take onthe value specified by <i>level</i>. Interrupts are locked out at or belowthat level. The value of <i>level</i> must be in the following range:<p><table><tr valign=top><td align=left> MC680x0: </td><td align=left> </td><td align=left> 0 - 7</tr><tr valign=top><td align=left> SH: </td><td align=left> </td><td align=left> 0 - 15</tr><tr valign=top><td align=left> ARM: </td><td align=left> </td><td align=left> BSP-specific</tr><tr valign=top><td align=left> SimSolaris: </td><td align=left> </td><td align=left> 0 - 1</tr><tr valign=top><td align=left> x86: </td><td align=left> </td><td align=left> interrupt controller specific</tr><tr valign=top><td align=left></tr></tr></table>On x86 systems, there are no interrupt level in the processorand the external interrupt controller manages the interrupt level.Therefore this routine does nothing and returns OK always.<p></blockquote><h4>NOTE SIMNT</h4><blockquote><p><p>This routine does nothing.<p></blockquote><h4>WARNING</h4><blockquote><p>Do not call VxWorks system routines with interrupts locked.Violating this rule may re-enable interrupts unpredictably.<p></blockquote><h4>RETURNS</h4><blockquote><p>The previous interrupt level.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./intArchLib.html#top">intArchLib</a></b><hr><a name="intLock"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>intLock( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>intLock( )</strong> - lock out interrupts</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>int intLock (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine disables interrupts. The <b><a href="./intArchLib.html#intLock">intLock</a>( )</b> routine returns anarchitecture-dependent lock-out key representing the interrupt levelprior to the call; this key can be passed to <b><a href="./intArchLib.html#intUnlock">intUnlock</a>( )</b> tore-enable interrupts.<p>For MC680x0, x86, and SH architectures, interruptsare disabled at the level set by <b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>( )</b>. The defaultlock-out level is the highest interrupt level (MC680x0 = 7,x86 = 1, SH = 15). <p>For SimSolaris architecture, interrupts are masked. Lock-out level returnedis 1 if interrupts were already locked, 0 otherwise.<p>For SimNT, a windows semaphore is used to lock the interrupts.Lock-out level returned is 1 if interrupts were already locked, 0 otherwise.<p>For MIPS processors, interrupts are disabled at themaster lock-out level; this means no interrupt can occur even ifunmasked in the IntMask bits (15-8) of the status register.<p>For ARM processors, interrupts (IRQs) are disabled by setting the I bitin the CPSR. This means no IRQs can occur.<p>For PowerPC processors, there is only one interrupt vector. The externalinterrupt (vector offset 0x500) is disabled when <b><a href="./intArchLib.html#intLock">intLock</a>( )</b> is called; thismeans that the processor cannot be interrupted by any external event.<p></blockquote><h4>IMPLEMENTATION</h4><blockquote><p>The lock-out key is implemented differently for different architectures:<p><table><tr valign=top><td align=left> MC680x0: </td><td align=left> interrupt field mask</tr><tr valign=top><td align=left> MIPS: </td><td align=left> status register</tr><tr valign=top><td align=left> x86: </td><td align=left> interrupt enable flag (IF) bit from EFLAGS register</tr><tr valign=top><td align=left> PowerPC: </td><td align=left> MSR register value</tr><tr valign=top><td align=left> ARM </td><td align=left> I bit from the CPSR</tr><tr valign=top><td align=left> SH: </td><td align=left> status register</tr><tr valign=top><td align=left> SimSolaris: </td><td align=left> 1 or 0 </tr><tr valign=top><td align=left> SimNT: </td><td align=left> 1 or 0 </tr><tr valign=top><td align=left></tr></tr></table></blockquote><h4>WARNINGS</h4><blockquote><p>Do not call VxWorks system routines with interrupts locked.Violating this rule may re-enable interrupts unpredictably.<p>The routine <b><a href="./intArchLib.html#intLock">intLock</a>( )</b> can be called from either interrupt or task level.When called from a task context, the interrupt lock level is part of thetask context. Locking out interrupts does not prevent rescheduling.Thus, if a task locks out interrupts and invokes kernel services thatcause the task to block (e.g., <b><a href="./taskLib.html#taskSuspend">taskSuspend</a>( )</b> or <b><a href="./taskLib.html#taskDelay">taskDelay</a>( )</b>) or that cause ahigher priority task to be ready (e.g., <b><a href="./semLib.html#semGive">semGive</a>( )</b> or <b><a href="./taskLib.html#taskResume">taskResume</a>( )</b>), thenrescheduling occurs and interrupts are unlocked while other tasksrun. Rescheduling may be explicitly disabled with <b><a href="./taskLib.html#taskLock">taskLock</a>( )</b>.Traps must be enabled when calling this routine.<p></blockquote><h4>EXAMPLES</h4><blockquote><p><pre> lockKey = intLock (); ... (work with interrupts locked out) intUnlock (lockKey);</pre>To lock out interrupts and task scheduling as well (see WARNING above):<pre> if (taskLock() == OK) { lockKey = intLock (); ... (critical section) intUnlock (lockKey); taskUnlock(); } else { ... (error message or recovery attempt) }</pre></blockquote><h4>RETURNS</h4><blockquote><p>An architecture-dependent lock-out key for the interrupt levelprior to the call.<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intUnlock">intUnlock</a>( )</b>, <b><a href="./taskLib.html#taskLock">taskLock</a>( )</b>, <b><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a>( )</b><hr><a name="intUnlock"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>intUnlock( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>intUnlock( )</strong> - cancel interrupt locks</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void intUnlock ( int lockKey /* lock-out key returned by preceding intLock() */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine re-enables interrupts that have been disabled by <b><a href="./intArchLib.html#intLock">intLock</a>( )</b>.The parameter <i>lockKey</i> is an architecture-dependent lock-out keyreturned by a preceding <b><a href="./intArchLib.html#intLock">intLock</a>( )</b> call.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><a href="./intArchLib.html#intLock">intLock</a>( )</b><hr><a name="intEnable"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>intEnable( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>intEnable( )</strong> - enable corresponding interrupt bits (MIPS, PowerPC, ARM)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>int intEnable ( int level /* new interrupt bits (0x00 - 0xff00) */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine enables the input interrupt bits on the present statusregister of the MIPS and PowerPC processors.<p></blockquote><h4>NOTE ARM</h4><blockquote><p><p>ARM processors generally do not have on-chip interrupt controllers.Control of interrupts is a BSP-specific matter. This routine calls aBSP-specific routine to enable the interrupt. For each interruptlevel to be used, there must be a call to this routine before it willbe allowed to interrupt.<p></blockquote><h4>NOTE MIPS</h4><blockquote><p><p>For MIPS, it is strongly advised that the level be a combination of<b>SR_IBIT1</b> - <b>SR_IBIT8</b>.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK or ERROR. (MIPS: The previous contents of the status register).</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./intArchLib.html#top">intArchLib</a></b><hr><a name="intDisable"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>intDisable( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>intDisable( )</strong> - disable corresponding interrupt bits (MIPS, PowerPC, ARM)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>int intDisable (⌨️ 快捷键说明
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