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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/pentiumLib.html - generated by refgen from ../i86/pentiumLib.c --> <title> pentiumLib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference : OS Libraries</i></a></p></blockquote><h1>pentiumLib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumLib</strong> - Pentium and Pentium[234] library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./pentiumLib.html#pentiumMtrrEnable">pentiumMtrrEnable</a>( )</b> - enable MTRR (Memory Type Range Register)<br><b><a href="./pentiumLib.html#pentiumMtrrDisable">pentiumMtrrDisable</a>( )</b> - disable MTRR (Memory Type Range Register)<br><b><a href="./pentiumLib.html#pentiumMtrrGet">pentiumMtrrGet</a>( )</b> - get MTRRs to a specified MTRR table<br><b><a href="./pentiumLib.html#pentiumMtrrSet">pentiumMtrrSet</a>( )</b> - set MTRRs from specified MTRR table with WRMSR instruction.<br><b><a href="./pentiumLib.html#pentiumPmcStart">pentiumPmcStart</a>( )</b> - start both PMC0 and PMC1<br><b><a href="./pentiumLib.html#pentiumPmcStart0">pentiumPmcStart0</a>( )</b> - start PMC0<br><b><a href="./pentiumLib.html#pentiumPmcStart1">pentiumPmcStart1</a>( )</b> - start PMC1<br><b><a href="./pentiumLib.html#pentiumPmcStop">pentiumPmcStop</a>( )</b> - stop both PMC0 and PMC1<br><b><a href="./pentiumLib.html#pentiumPmcStop0">pentiumPmcStop0</a>( )</b> - stop PMC0<br><b><a href="./pentiumLib.html#pentiumPmcStop1">pentiumPmcStop1</a>( )</b> - stop PMC1<br><b><a href="./pentiumLib.html#pentiumPmcGet">pentiumPmcGet</a>( )</b> - get the contents of PMC0 and PMC1<br><b><a href="./pentiumLib.html#pentiumPmcGet0">pentiumPmcGet0</a>( )</b> - get the contents of PMC0<br><b><a href="./pentiumLib.html#pentiumPmcGet1">pentiumPmcGet1</a>( )</b> - get the contents of PMC1<br><b><a href="./pentiumLib.html#pentiumPmcReset">pentiumPmcReset</a>( )</b> - reset both PMC0 and PMC1<br><b><a href="./pentiumLib.html#pentiumPmcReset0">pentiumPmcReset0</a>( )</b> - reset PMC0<br><b><a href="./pentiumLib.html#pentiumPmcReset1">pentiumPmcReset1</a>( )</b> - reset PMC1<br><b><a href="./pentiumLib.html#pentiumMsrInit">pentiumMsrInit</a>( )</b> - initialize all the MSRs (Model Specific Register)<br><b><a href="./pentiumLib.html#pentiumMcaEnable">pentiumMcaEnable</a>( )</b> - enable/disable the MCA (Machine Check Architecture)<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library provides Pentium and Pentium[234] specific routines. <p></blockQuote><h4>MTRR (Memory Type Range Register)</h4><blockQuote>MTRR (Memory Type Range Register) are a new feature introduced in the P6 family processor that allow the processor to optimize memory operationsfor different types of memory, such as RAM, ROM, frame buffer memory, andmemory-mapped IO. MTRRs configure an internal map of how physical address ranges are mapped to various types of memory. The processor uses this internalmap to determine the cacheability of various physical memory locations and theoptimal method of accessing memory locations. For example, if a memorylocation is specified in an MTRR as write-through memory, the processor handlesaccesses to this location as follows. It reads data from that location in lines and caches the read data or maps all writes to that location to the busand updates the cache to maintain cache coherency. In mapping the physicaladdress space with MTRRs, the processor recognizes five types of memory:uncacheable (UC), write-combining (WC), write-through (WT),write-protected (WP), and write-back (WB).<p>There is one table - sysMtrr[] in <b>sysLib.c</b> - and four routines to interfacethe MTRR. These four routines are:<pre> void pentiumMtrrEnable (void) void pentiumMtrrDisable (void) STATUS pentiumMtrrGet ( MTRR * pMtrr /* MTRR table */ ) STATUS pentiumMtrrSet (void) ( MTRR * pMtrr /* MTRR table */ )</pre><b><a href="./pentiumLib.html#pentiumMtrrEnable">pentiumMtrrEnable</a>( )</b> enables MTRR, <b><a href="./pentiumLib.html#pentiumMtrrDisable">pentiumMtrrDisable</a>( )</b> disables MTRR.<b><a href="./pentiumLib.html#pentiumMtrrGet">pentiumMtrrGet</a>( )</b> gets MTRRs to the specified MTRR table.<b><a href="./pentiumLib.html#pentiumMtrrGet">pentiumMtrrGet</a>( )</b> sets MTRRs from the specified MTRR table.The MTRR table is defined as follows:<pre>typedef struct mtrr_fix /* MTRR - fixed range register */ { char type[8]; /* address range: [0]=0-7 ... [7]=56-63 */ } MTRR_FIX;typedef struct mtrr_var /* MTRR - variable range register */ { long long int base; /* base register */ long long int mask; /* mask register */ } MTRR_VAR;typedef struct mtrr /* MTRR */ { int cap[2]; /* MTRR cap register */ int deftype[2]; /* MTRR defType register */ MTRR_FIX fix[11]; /* MTRR fixed range registers */ MTRR_VAR var[8]; /* MTRR variable range registers */ } MTRR;</pre>Fixed Range Register's type array can be one of following memory types.<b>MTRR_UC</b> (uncacheable), <b>MTRR_WC</b> (write-combining), <b>MTRR_WT</b> (write-through), <b>MTRR_WP</b> (write-protected), and <b>MTRR_WB</b> (write-back).MTRR is enabled in <b><a href="./sysLib.html#sysHwInit">sysHwInit</a>( )</b>.<p></blockQuote><h4>PMC (Performance Monitoring Counters)</h4><blockQuote>The P5 and P6 family of processors has two performance-monitoring countersfor use in monitoring internal hardware operations. These counters areduration or event counters that can be programmed to count any of approximately100 different types of events, such as the number of instructions decoded,number of interrupts received, or number of cache loads. However, the set ofevents can be counted with PMC is different in the P5 and P6 family ofprocessors; and the locations and bit difinitions of the related counter andcontrol registers are also different. So there are two set of PMC routines,one for P6 family and one for P5 family respectively in <b><a href="./pentiumALib.html#top">pentiumALib</a></b>. Forconvenience, the PMC routines here are acting as wrappers to those routinesin <b><a href="./pentiumALib.html#top">pentiumALib</a></b>. They will call the P5 or P6 routine depending on the processor type.<p>There are twelve routines to interface the PMC. These twelve routines are:<pre> STATUS pentiumPmcStart ( int pmcEvtSel0; /* performance event select register 0 */ int pmcEvtSel1; /* performance event select register 1 */ ) STATUS pentiumPmcStart0 ( int pmcEvtSel0; /* performance event select register 0 */ ) STATUS pentiumPmcStart1 ( int pmcEvtSel1; /* performance event select register 1 */ ) void pentiumPmcStop (void) void pentiumPmcStop0 (void) void pentiumPmcStop1 (void) void pentiumPmcGet ( long long int * pPmc0; /* performance monitoring counter 0 */ long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumPmcGet0 ( long long int * pPmc0; /* performance monitoring counter 0 */ ) void pentiumPmcGet1 ( long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumPmcReset (void) void pentiumPmcReset0 (void) void pentiumPmcReset1 (void)</pre><b><a href="./pentiumLib.html#pentiumPmcStart">pentiumPmcStart</a>( )</b> starts both PMC0 and PMC1. <b><a href="./pentiumLib.html#pentiumPmcStart0">pentiumPmcStart0</a>( )</b> starts PMC0,and <b><a href="./pentiumLib.html#pentiumPmcStart1">pentiumPmcStart1</a>( )</b> starts PMC1.<b><a href="./pentiumLib.html#pentiumPmcStop">pentiumPmcStop</a>( )</b> stops both PMC0 and PMC1. <b><a href="./pentiumLib.html#pentiumPmcStop0">pentiumPmcStop0</a>( )</b> stops PMC0, and <b><a href="./pentiumLib.html#pentiumPmcStop1">pentiumPmcStop1</a>( )</b> stops PMC1.<b><a href="./pentiumLib.html#pentiumPmcGet">pentiumPmcGet</a>( )</b> gets contents of PMC0 and PMC1. <b><a href="./pentiumLib.html#pentiumPmcGet0">pentiumPmcGet0</a>( )</b> getscontents of PMC0, and <b><a href="./pentiumLib.html#pentiumPmcGet1">pentiumPmcGet1</a>( )</b> gets contents of PMC1.<b><a href="./pentiumLib.html#pentiumPmcReset">pentiumPmcReset</a>( )</b> resets both PMC0 and PMC1. <b><a href="./pentiumLib.html#pentiumPmcReset0">pentiumPmcReset0</a>( )</b> resetsPMC0, and <b><a href="./pentiumLib.html#pentiumPmcReset1">pentiumPmcReset1</a>( )</b> resets PMC1.PMC is enabled in <b><a href="./sysLib.html#sysHwInit">sysHwInit</a>( )</b>. Selected events in the default configurationare PMC0 = number of hardware interrupts received and PMC1 = number ofmisaligned data memory references.<p></blockQuote><h4>MSR (Model Specific Registers)</h4><blockQuote>The P5(Pentium), P6(PentiumPro, II, III), and P7(Pentium4) family processorscontain a model-specific registers (MSRs). These registers are implement-ation specific. They are provided to control a variety of hardware and software related features including the performance monitoring, the debugextensions, the machine check architecture, etc.<p>There is one routine - <b><a href="./pentiumLib.html#pentiumMsrInit">pentiumMsrInit</a>( )</b> - to initialize all the MSRs.This routine initializes all the MSRs in the processor and works on eitherP5, P6 or P7 family processors.<p></blockQuote><h4>MCA (Machine Check Architecture)</h4><blockQuote>The P5(Pentium), P6(PentiumPro, II, III), and P7(Pentium4) family processorshave a machine-check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as system bus errors, ECCerrors, parity errors, cache errors and TLB errors. It consists of a setof model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs for recording errors that are detected.The processor signals the detection of a machine-check error by generatinga machine-check exception, which an abort class exception. The implement-ation of the machine-check architecture, does not ordinarily permit the processor to be restarted reliably after generating a machine-check exception. However, the machine-check exception handler can collectinformation about the machine-check error from the machine-check MSRs.<p>There is one routine - <b><a href="./pentiumLib.html#pentiumMcaEnable">pentiumMcaEnable</a>( )</b> - to enable or disable the MCA.The routine enables or disables 1) the Machine Check Architecture and its Error Reporting register banks 2) the Machine Check Exception by togglingthe MCE bit in the CR4. This routine works on either P5, P6 or P7 family.<p></blockquote><h4>SEE ALSO</h4><blockquote><p><p><i><b>PentiumALib</b>, Pentium, Pentium[234] Family Developer's Manual"</i><hr><a name="pentiumMtrrEnable"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumMtrrEnable( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumMtrrEnable( )</strong> - enable MTRR (Memory Type Range Register)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void pentiumMtrrEnable (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine enables the MTRR that provide a mechanism for associating thememory types with physical address ranges in system memory.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumLib.html#top">pentiumLib</a></b><hr><a name="pentiumMtrrDisable"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumMtrrDisable( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumMtrrDisable( )</strong> - disable MTRR (Memory Type Range Register)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void pentiumMtrrDisable (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine disables the MTRR that provide a mechanism for associating thememory types with physical address ranges in system memory.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumLib.html#top">pentiumLib</a></b><hr><a name="pentiumMtrrGet"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumMtrrGet( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumMtrrGet( )</strong> - get MTRRs to a specified MTRR table</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS pentiumMtrrGet ( MTRR * pMtrr /* MTRR table */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine gets MTRRs to a specified MTRR table with RDMSR instruction.The read MTRRs are CAP register, DEFTYPE register, fixed range MTRRs, andvariable range MTRRs.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR if MTRR is being accessed.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumLib.html#top">pentiumLib</a></b><hr><a name="pentiumMtrrSet"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumMtrrSet( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumMtrrSet( )</strong> - set MTRRs from specified MTRR table with WRMSR instruction.</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS pentiumMtrrSet ( MTRR * pMtrr /* MTRR table */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine sets MTRRs from specified MTRR table with WRMSR instruction.The written MTRRs are DEFTYPE register, fixed range MTRRs, and variablerange MTRRs.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR if MTRR is enabled or being accessed.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./pentiumLib.html#top">pentiumLib</a></b><hr><a name="pentiumPmcStart"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>pentiumPmcStart( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>pentiumPmcStart( )</strong> - start both PMC0 and PMC1</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS pentiumPmcStart (pmcEvtSel0, pmcEvtSel1)⌨️ 快捷键说明
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