cachesh7750lib.html

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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/cacheSh7750Lib.html - generated by refgen from ../sh/cacheSh7750Lib.c --> <title> cacheSh7750Lib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference :  OS Libraries</i></a></p></blockquote><h1>cacheSh7750Lib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  <p><strong>cacheSh7750Lib</strong> - Hitachi SH7750 cache management library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./cacheSh7750Lib.html#cacheSh7750LibInit">cacheSh7750LibInit</a>(&nbsp;)</b>  -  initialize the SH7750 cache library<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains architecture-specific cache library functions forthe Hitachi SH7750 architecture.  There is a 8-Kbyte instruction cache and16-Kbyte operand cache that operates in write-through or write-back (copyback)mode.  The 16-Kbyte operand cache can be divided into 8-Kbyte cache and8-Kbyte memory.  Cache line size is fixed at 32 bytes,and the cache address array holds physical addresses as cache tags.Cache entries may be "flushed" by accesses to the address array in privilegedmode.  There is a write-back buffer which can hold one line of cache entry,and the completion of write-back cycle is assured by accessing to any cachethrough region.<p>For general information about caching, see the manual entry for <b><a href="./cacheLib.html#top">cacheLib</a></b>.<p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>cacheLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheLib.html#top">cacheLib</a></b><hr><a name="cacheSh7750LibInit"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries :  Routines</i></a></p></blockquote><h1>cacheSh7750LibInit(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  <p><strong>cacheSh7750LibInit(&nbsp;)</strong> - initialize the SH7750 cache library</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS cacheSh7750LibInit    (    CACHE_MODE instMode,      /* instruction cache mode */    CACHE_MODE dataMode       /* data cache mode */    )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine initializes the cache library for the Hitachi SH7750 processor.It initializes the function pointers and configures the caches to thespecified cache modes.  Modes should be set before caching is enabled.If two complementary flags are set (enable/disable), no action is takenfor any of the input flags.<p>The following caching modes are available for the SH7750 processor:<p><table><tr valign=top><td align=left></td><td align=left> SH7750:</td><td align=left> <b>CACHE_WRITETHROUGH</b>  </td><td align=left></tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_COPYBACK</b>      </td><td align=left> (copy-back cache for P0/P3, data cache only)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_COPYBACK_P1</b>   </td><td align=left> (copy-back cache for P1, data cache only)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_RAM_MODE</b>      </td><td align=left> (use half of cache as RAM, data cache only)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_2WAY_MODE</b>     </td><td align=left> (use RAM in 2way associ. mode, data cache only)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_A25_INDEX</b>     </td><td align=left> (use A25 as MSB of cache index)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_DMA_BYPASS_P0</b> </td><td align=left> (allocate DMA buffer to P2, free it to P0)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_DMA_BYPASS_P1</b> </td><td align=left> (allocate DMA buffer to P2, free it to P1)</tr><tr valign=top><td align=left></td><td align=left>        </td><td align=left> <b>CACHE_DMA_BYPASS_P3</b> </td><td align=left> (allocate DMA buffer to P2, free it to P3)</tr><tr valign=top><td align=left></tr></tr></table>The <b>CACHE_DMA_BYPASS_Px</b> modes allow to allocate "cache-safe" buffers withoutMMU.  If none of <b>CACHE_DMA_BYPASS_Px</b> modes is specified, <b><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a>(&nbsp;)</b>returns a cache-safe buffer on logical space, which is created by the MMU.If <b>CACHE_DMA_BYPASS_P0</b> is selected, <b><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a>(&nbsp;)</b> returns a cache-safebuffer on P2 space, and <b><a href="./cacheLib.html#cacheDmaFree">cacheDmaFree</a>(&nbsp;)</b> releases the buffer to P0 space.Namely, if the system memory partition is located on P0, cache-safe bufferscan be allocated and freed without MMU, by selecting <b>CACHE_DMA_BYPASS_P0</b>.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR if specified cache mode is invalid.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheSh7750Lib.html#top">cacheSh7750Lib</a></b></body></html>

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