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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/cacheSh7729Lib.html - generated by refgen from ../sh/cacheSh7729Lib.c --> <title> cacheSh7729Lib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.htm"><i>VxWorks API Reference : OS Libraries</i></a></p></blockquote><h1>cacheSh7729Lib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheSh7729Lib</strong> - Hitachi SH7729 cache management library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><a href="./cacheSh7729Lib.html#cacheSh7729LibInit">cacheSh7729LibInit</a>( )</b> - initialize the SH7729 cache library<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains architecture-specific cache library functions forthe Hitachi SH7729 architecture.<p>The cache is 16-Kbytes (16 bytes X 256 entries X 4 ways) mixed instructionand data cache that operates in write-through or write-back (copyback) mode.Cache line size is fixed at 16 bytes, and the cache address array holds physical addresses as cache tags. Cache entries may be "flushed" by accessesto the address array in privileged mode. There is a write-back buffer whichcan hold one line of cache entry, and the completion of write-back cycle isassured by accessing to any cache through region.<p>For general information about caching, see the manual entry for <b><a href="./cacheLib.html#top">cacheLib</a></b>.<p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>cacheLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheLib.html#top">cacheLib</a></b><hr><a name="cacheSh7729LibInit"></a><p align=right><a href="rtnIndex.htm"><i>OS Libraries : Routines</i></a></p></blockquote><h1>cacheSh7729LibInit( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheSh7729LibInit( )</strong> - initialize the SH7729 cache library</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS cacheSh7729LibInit ( CACHE_MODE instMode, /* instruction cache mode (ignored) */ CACHE_MODE dataMode /* data cache mode */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine initializes the cache library for the Hitachi SH7729 processor.It initializes the function pointers and configures the caches to thespecified cache modes. Modes should be set before caching is enabled.If two complementary flags are set (enable/disable), no action is takenfor any of the input flags.<p>The following caching modes are available for the SH7729 processor:<p><table><tr valign=top><td align=left></td><td align=left> SH7729:</td><td align=left> <b>CACHE_WRITETHROUGH</b> </td><td align=left> (cache for instruction and data)</tr><tr valign=top><td align=left></td><td align=left> </td><td align=left> <b>CACHE_COPYBACK</b> </td><td align=left> (cache for instruction and data)</tr><tr valign=top><td align=left></td><td align=left> </td><td align=left> <b>CACHE_COPYBACK_P1</b> </td><td align=left> (copy-back cache for P1)</tr><tr valign=top><td align=left></td><td align=left> </td><td align=left> <b>CACHE_DMA_BYPASS_P0</b> </td><td align=left> (allocate DMA buffer to P2, free it to P0)</tr><tr valign=top><td align=left></td><td align=left> </td><td align=left> <b>CACHE_DMA_BYPASS_P1</b> </td><td align=left> (allocate DMA buffer to P2, free it to P1)</tr><tr valign=top><td align=left></td><td align=left> </td><td align=left> <b>CACHE_DMA_BYPASS_P3</b> </td><td align=left> (allocate DMA buffer to P2, free it to P3)</tr><tr valign=top><td align=left></tr></tr></table>The <b>CACHE_DMA_BYPASS_Px</b> modes allow to allocate "cache-safe" buffers withoutMMU. If none of <b>CACHE_DMA_BYPASS_Px</b> modes is specified, <b><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a>( )</b>returns a cache-safe buffer on logical space, which is created by the MMU.If <b>CACHE_DMA_BYPASS_P0</b> is selected, <b><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a>( )</b> returns a cache-safebuffer on P2 space, and <b><a href="./cacheLib.html#cacheDmaFree">cacheDmaFree</a>( )</b> releases the buffer to P0 space.Namely, if the system memory partition is located on P0, cache-safe bufferscan be allocated and freed without MMU, by selecting <b>CACHE_DMA_BYPASS_P0</b>.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheSh7729Lib.html#top">cacheSh7729Lib</a></b></body></html>⌨️ 快捷键说明
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