configurable_rgb_to_yuv.v

根据输出显示模式不同可以选择不同的色度转换模式

  if(~ngreset)
	begin
	temp1_d3_a <= 10'h3ff;
	temp1_d3_b <= 10'h3ff;
	end
  else
	begin	
	temp1_d3_a <= {1'b0,temp1_d2[8:0]} + {1'b0,g22_2[8:0]};
	temp1_d3_b <= {2'b00,temp1_d2[14:9]} + {2'b00,g22_2[14:9]};
	end

wire[7:0]	temp1_d4;
assign  temp1_d4 = temp1_d3_b[7:0] + temp1_d3_a[9];
  
reg[10:0]	rg1_b;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	rg1_b <= 11'h7ff;
  else
	begin	
	if(temp1_d4 > temp1_d1[16:9])
        	rg1_b <= {1'b0,temp1_d4,temp1_d3_a[8:7]} - {1'b0,temp1_d1[16:7]};
	else if(temp1_d4 < temp1_d1[16:9])
                rg1_b <= {1'b1,temp1_d1[16:7]} - {1'b0,temp1_d4,temp1_d3_a[8:7]};
	else
        	begin
        	if(temp1_d3_a[8:0] >= temp1_d1[8:0])
                       rg1_b <= {1'b0,temp1_d4,temp1_d3_a[8:7]} - {1'b0,temp1_d1[16:7]};
        	else
                       rg1_b <= {1'b1,temp1_d1[16:7]} - {1'b0,temp1_d4,temp1_d3_a[8:7]};
        	end
	end

wire[9:0]	cb2_rgb;
reg[7:0]	cb2_temp;        
assign	cb2_rgb = rg1_b[10:1];        
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	cb2_temp <= 8'h00;
  else
	begin
	if(~cb2_rgb[9])
        	begin
        	if(cb2_rgb[9:0]>=8'd127)
                	cb2_temp <= 8'hff;
        	else
                	cb2_temp <= cb2_rgb[7:0] + 8'd128;
        	end
	else
        	begin
        	if(cb2_rgb[9:0]>=8'd128)
                	cb2_temp <= 8'h00;
        	else
                	cb2_temp <= 8'd128 - cb2_rgb[7:0];
        	end
	end
//-------------------------step2 end-----------------------------//	
	
//------------------------------------------------------------//
//                step3 convert rgb to Cr_out                 //
//------------------------------------------------------------// 
//Cr
reg[15:0]	r23_1;//(128+2)R  +
reg[10:0]	rb23_1;//R+4B  +
reg[11:0]	g23_1;//(8+1)G---+
reg[15:0]       gb23_1;//128G+16B  -
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	r23_1 <= 16'hffff;
	rb23_1 <= 11'h7ff;
	g23_1 <= 12'hfff;
	gb23_1 <= 16'hffff;
	end
  else
	begin	
	r23_1 <= {1'b0,r_in,7'b0000000} + {7'b0000000,r_in,1'b0};
	rb23_1 <= {3'b000,r_in} + {1'b0,b_in,2'b00};
	g23_1 <= {1'b0,g_in,3'b000} + {4'b0000,g_in};
	gb23_1 <= {1'b0,g_in,7'b0000000} + {6'b000000,g_in,2'b00};
	end

reg[12:0]	temp2_d1;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	temp2_d1 <= 13'h1fff;
  else	
	temp2_d1 <= {2'b00,rb23_1} + {1'b0,g23_1};

reg[9:0]	temp2_d2_a;
reg[7:0]        temp2_d2_b;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	temp2_d2_a <= 10'h3ff;
	temp2_d2_b <= 8'hff;
	end
  else
	begin
	temp2_d2_a <= {1'b0,r23_1[8:0]} + {1'b0,temp2_d1[8:0]};
	temp2_d2_b <= {2'b00,r23_1[15:9]} + {4'b0000,temp2_d1[12:9]};
	end
wire[7:0]	temp2_d2_b2;
assign  temp2_d2_b2 =  temp2_d2_b[7:0] + temp2_d2_a[9]; //temp2_d2_a[8:0]; 

reg[10:0]	temp2_d3;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	temp2_d3 <= 12'hfff;
  else
	begin	
	if(temp2_d2_b2 > gb23_1[15:9])
        	temp2_d3 <= {1'b0,temp2_d2_b2,temp2_d2_a[8:7]} - {2'b00,gb23_1[15:7]};
	else if(temp2_d2_b2 < gb23_1[15:9])
                temp2_d3 <= {2'b10,gb23_1[15:7]} - {1'b0,temp2_d2_b2,temp2_d2_a[8:7]};
	else
                begin
        	if(temp2_d2_a[8:0] >= gb23_1[8:0])
                	temp2_d3 <= {1'b0,temp2_d2_b2,temp2_d2_a[8:7]} - {2'b00,gb23_1[16:7]};
        	else
                	temp2_d3 <= {2'b10,gb23_1[16:7]} - {1'b0,temp2_d2_b2,temp2_d2_a[8:7]};
        	end
	end 

wire[9:0]	cr2_rgb;
reg[7:0]	cr2_temp;        
assign	cr2_rgb = temp2_d3[10:1];        
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	cr2_temp <= 8'h00;
  else
	begin
	if(~cr2_rgb[9])
        	begin
        	if(cr2_rgb[8:0]>=8'd127)
                	cr2_temp <= 8'hff;
        	else
                	cr2_temp <= cr2_rgb[7:0] + 8'd128;
        	end
	else
        	begin
        	if(cr2_rgb[8:0]>=8'd128)
                	cr2_temp <= 8'h00;
        	else
                	cr2_temp <= 8'd128 - cr2_rgb[7:0];
        	end
	end
	
//-------------------result  -------------------------------------//


reg[7:0] y2_out,uv2_out;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	y2_out <= 8'h00;
	uv2_out <= 8'h80;
	end
  else
	begin
	y2_out <= y2_temp;
	if(select_uv)
        	uv2_out <= cb2_temp;
	else
        	uv2_out <= cr2_temp;
	end

reg[7:0] y2_data,u2_data,v2_data;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
          y2_data <= 8'h00;
          u2_data <= 8'h80;
          v2_data <= 8'h80;
	end
  else
	begin
          y2_data <= y2_temp;
          u2_data <= cb2_temp;
          v2_data <= cr2_temp;
	end
	
//------------------------------------------------------------------

//******************************************************************//
//                    converter3: PC                             //
//*****************************************************************//

//------------------------------------------------------------//
//                step1 convert rgb to y_out                 //
//------------------------------------------------------------// 
//y_out
reg[14:0]	r3_1;//(64+8)R
reg[10:0]	r3_2;//(4+1)R
reg[15:0]	g3_1;//(128+16)G
reg[10:0]	g3_2;//(4+2)G
reg[12:0]	b3_1;//(16+8)B
reg[10:0]       b3_2;//(4+1)B
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	r3_1 <= 15'h7fff;
	r3_2 <= 11'h7ff;
	g3_1 <= 16'hffff;
	g3_2 <= 11'h7ff;
	b3_1 <= 13'h1fff;
	b3_2 <= 11'h7ff;
	end
  else
	begin	
	r3_1 <= {1'b0,r_in,6'b000000} + {4'b0000,r_in,3'b000};
	r3_2 <= {1'b0,r_in,2'b00} + {3'b000,r_in};
	g3_1 <= {1'b0,g_in,7'b0000000} + {4'b0000,g_in,4'b0000};
	g3_2 <= {1'b0,g_in,2'b00} + {2'b00,g_in,1'b0};//-
	b3_1 <= {1'b0,b_in,4'b0000} + {2'b00,b_in,3'b000};
	b3_2 <= {1'b0,b_in,2'b00} + {3'b000,b_in};
	end

reg[15:0]	temp3_d1;//r3_1+r3_2
reg[16:0]	temp3_d2;//g3_1+g3_2
reg[13:0]       temp3_d3;//b3_1+b3_2
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	temp3_d1 <= 16'hffff;
	temp3_d2 <= 17'h1ffff;
	temp3_d3 <= 14'h3fff;
	end
  else
	begin	
	temp3_d1 <= {1'b0,r3_1} + {5'b00000,r3_2};
	temp3_d2 <= {1'b0,g3_1} + {6'b000000,g3_2};
	temp3_d3 <= {1'b0,b3_1} + {3'b000,b3_2};
	end

reg[16:0]	temp3_d4;//r2_3+gb_1
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	temp3_d4 <= 17'h1ffff;
  else	
	temp3_d4 <= {1'b0,temp3_d1} + {3'b000,temp3_d3};
	
reg[17:0]  r3_d1;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
        r3_d1 <= 18'h3ffff;
  else
        r3_d1 <= {1'b0,temp3_d2} + {1'b0,temp3_d3};
 	
reg[7:0]	y3_temp; 
wire[9:0] y3_rgb;             
assign		y3_rgb = r3_d1[17:8];
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	y3_temp <= 8'h00;
  else
	begin
	if(y3_rgb[9:0]>=8'd255)
        	y3_temp <= 8'hff;
	else
        	y3_temp <= y3_rgb[7:0];
	end

//-----------------------------------------------------------------------------

//------------------------------------------------------------//
//                step2 convert rgb to Cb_out                 //
//------------------------------------------------------------//         
//Cb
reg[13:0]	r32_1;//(32+4)R  -
reg[14:0]	g32_1;//(64+8)G  -
reg[9:0]	rg32_1;//2R+2G -
reg[14:0]	b32_1;//(64+32)B +
reg[11:0]	b32_2;//16B +
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	r32_1 <= 14'h3fff;
	g32_1 <= 15'h7fff;
	rg32_1 <= 10'h3ff;
	b32_1 <= 15'h7fff;
	b32_2 <= 12'hfff;
	end
  else
	begin	
	r32_1 <= {1'b0,r_in,5'b00000} + {4'b0000,r_in,4'b0000};//位对齐
	g32_1 <= {1'b0,g_in,6'b000000} + {4'b0000,g_in,3'b000};
	rg32_1 <= {1'b0,r_in,1'b0} + {1'b0,g_in,1'b0};
	b32_1 <= {1'b0,b_in,6'b000000} + {2'b00,b_in,5'b00000};
	b32_2 <= {b_in,4'b0000};
	end

reg[14:0]	temp32_d1;//r32_1+rg32_1
reg[15:0]	temp32_d2;//b32_1+b32_2
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	temp32_d1 <= 15'h7fff;
	temp32_d2 <= 16'hffff;
	end
  else
	begin	
	temp32_d1 <= {1'b0,r32_1} + {5'b00000,rg32_1};//-
	temp32_d2 <= {1'b0,b32_1} + {4'b0000,b32_2};//+
	end

reg[9:0]	temp32_d3_a;
reg[7:0]        temp32_d3_b;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	temp32_d3_a <= 10'h3ff;
	temp32_d3_b <= 10'h3ff;
	end
  else
	begin	
	temp32_d3_a <= {1'b0,temp32_d1[8:0]} + {1'b0,g32_1[8:0]};
	temp32_d3_b <= {2'b00,temp32_d1[14:9]} + {2'b00,g32_1[14:9]};
	end

wire[7:0]	temp32_d4;
assign  temp32_d4 = temp32_d3_b[7:0] + temp32_d3_a[9];
  
reg[10:0]	rg2_b;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	rg2_b <= 11'h7ff;
  else
	begin	
	if(temp32_d4 < temp32_d2[15:9])
        	rg2_b <=  {2'b00,temp32_d2[15:7]} - {1'b0,temp32_d4,temp32_d3_a[8:7]};
	else if(temp1_d4 > temp1_d1[15:9])
                rg2_b <= {2'b10,temp32_d2[15:7]} - {1'b0,temp32_d4,temp32_d3_a[8:7]};
	else
        	begin
        	if(temp32_d3_a[8:0] <= temp32_d2[8:0])
                       rg2_b <= {2'b00,temp32_d2[15:7]} - {1'b0,temp32_d4,temp32_d3_a[8:7]};
        	else
                       rg2_b <= {2'b10,temp32_d2[15:7]} - {1'b0,temp32_d4,temp32_d3_a[8:7]};
        	end
	end

wire[9:0]	cb3_rgb;
reg[7:0]	cb3_temp;        
assign	cb3_rgb = rg2_b[10:1];        
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	cb3_temp <= 8'h00;
  else
	begin
	if(~cb3_rgb[9])
           cb3_temp <= cb3_rgb[7:0];
	else
           cb3_temp <= 8'h00;
	end
//-------------------------step2 end-----------------------------//	
	
//------------------------------------------------------------//
//                step3 convert rgb to Cr_out                 //
//------------------------------------------------------------// 
//Cr
reg[15:0]	r33_1;//(128+32)R  +
reg[10:0]	r33_2;//(2+1)R  -
reg[15:0]	g33_1;//(128+4)G-
reg[11:0]       b33_1;//(8+2)B  -
reg[11:0]       b33_2;//128B  -
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	r33_1 <= 16'hffff;
	r33_2 <= 11'h7ff;
	g33_1 <= 16'hffff;
	b33_1 <= 12'hfff;
	b33_2 <= 12'hfff;
	end
  else
	begin	
	r33_1 <= {1'b0,r_in,7'b0000000} + {3'b000,r_in,5'b00000};
	r33_2 <= {1'b0,r_in,1'b0} + {2'b00,b_in};
	g33_1 <= {1'b0,g_in,7'b0000000} + {6'b000000,g_in,2'b00};
	b33_1 <= {1'b0,b_in,3'b000} + {3'b000,g_in,1'b0};
	b33_2 <= {b_in,4'b0000};
	end
	
reg[16:0]       temp33_d1; 
reg[12:0]	temp33_d2;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
     begin
        temp33_d1 <= 17'h1ffff;
	temp33_d2 <= 13'h1fff;
     end
  else	
     begin
	temp33_d1 <= {1'b0,g33_1} + {6'b000000,r33_2};
	temp33_d2 <= {1'b0,b33_1} + {1'b0,b33_2};
     end

//reg[17:0]  temp33_d3;
//always @(posedge dclk or posedge ngreset)
//   if(~ngreset)
//      temp33_d3 <= 18'h3ffff;
//   else 
//      temp33_d3 <= {1'b0,temp33_d1} + {5'b00000,temp33_d2};
      
reg[9:0]	temp33_d2_a;
reg[7:0]        temp33_d2_b;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	temp33_d2_a <= 10'h3ff;
	temp33_d2_b <= 8'hff;
	end
  else
	begin
	temp33_d2_a <= {1'b0,temp33_d1[8:0]} + {1'b0,temp33_d2[8:0]};
	temp33_d2_b <= {2'b00,temp33_d1[15:9]} + {4'b0000,temp33_d2[12:9]};
	end
wire[7:0]	temp33_d2_b2;
assign  temp33_d2_b2 =  temp33_d2_b[7:0] + temp33_d2_a[9]; //temp33_d2_a[8:0]; 

reg[10:0]	temp33_d3;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	temp33_d3 <= 12'hfff;
  else
	begin	
	if(temp33_d2_b2 > r33_1[15:9])
        	temp33_d3 <= {1'b0,temp33_d2_b2,temp33_d2_a[8:7]} - {2'b00,r33_1[15:7]};
	else if(temp33_d2_b2 < r33_1[15:9])
                temp33_d3 <= {2'b10,r33_1[15:7]} - {1'b0,temp33_d2_b2,temp33_d2_a[8:7]};
	else
                begin
        	if(temp33_d2_a[8:0] >= r33_1[8:0])
                	temp33_d3 <= {1'b0,temp33_d2_b2,temp33_d2_a[8:7]} - {2'b00,r33_1[16:7]};
        	else
                	temp33_d3 <= {2'b10,r33_1[16:7]} - {1'b0,temp33_d2_b2,temp33_d2_a[8:7]};
        	end
	end 

wire[9:0]	cr3_rgb;
reg[7:0]	cr3_temp;        
assign	cr3_rgb = temp33_d3[10:1];        
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	cr3_temp <= 8'h00;
  else
	begin
	if(~cr3_rgb[9])
           cr3_temp <= cr3_rgb[7:0];
	else
           cr3_temp <= 8'h00;
	end
//------------- result  --------------------------

reg[7:0] y3_out,uv3_out;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
	y3_out <= 8'h00;
	uv3_out <= 8'h80;
	end
  else
	begin
	y3_out <= y3_temp;
	if(select_uv)
        	uv3_out <= cb3_temp;
	else
        	uv3_out <= cr3_temp;
	end

reg[7:0] y3_data,u3_data,v3_data;
always @(posedge dclk or negedge ngreset)
  if(~ngreset)
	begin
          y3_data <= 8'h00;
          u3_data <= 8'h80;
          v3_data <= 8'h80;
	end
  else
	begin
          y3_data <= y3_temp;
          u3_data <= cb3_temp;
          v3_data <= cr3_temp;
	end 
/****************************  converter 1-3 the end  ***************************************/

//-------------------output datas------------------------------//
reg[7:0] y_out_d1,uv_out_d1;
reg[7:0] y_data_d1,u_data_d1,v_data_d1;
always @(posedge dclk or negedge ngreset)
if(~ngreset)
begin
	   y_out_d1 <= 8'h00;
	   uv_out_d1 <= 8'h80;
	   y_data_d1 <= 8'h00;
	   u_data_d1 <= 8'h80;
	   v_data_d1 <= 8'h80;
end
else
begin
case(scontrl)
1'b00:
  begin
     y_out_d1 <= y1_out_d1;
     uv_out_d1 <= uv1_out;
     y_data_d1 = y1_data;
     u_data_d1 = u1_data;
     v_data_d1 = v1_data;         
  end
2'b01:
  begin
     y_out_d1 <= y2_out;
     uv_out_d1 <= uv2_out;
     y_data_d1 = y2_data;
     u_data_d1 = u2_data;
     v_data_d1 = v2_data;         
  end
default:
  begin
     y_out_d1 <= y3_out;
     uv_out_d1 <= uv3_out;
     y_data_d1 = y2_data;
     u_data_d1 = u2_data;
     v_data_d1 = v2_data;         
  end
endcase    
end

wire[7:0] y_out,uv_out;
wire[7:0] y_data,u_data,v_data;
assign    y_out = y_out_d1;
assign    uv_out = uv_out_d1;
assign    y_data = y_data_d1;
assign    u_data = u_data_d1;
assign    v_data = v_data_d1;    
endmodule