📄 configurable_rgb_to_yuv.v
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// ***************************Declaration*************************************************************** //// * * //// * File name: configurable_rgb_to_yuv.v * //// * Abstract: * //// * fuction: color space converter;RGB to YUV,8bit. * //// * first,RGB--->YUV4:4:4 format，then convert to 4:2:2 format * //// * * //// * converter1：rgb-->YUV/YCbCr SDTV * //// * Y = (0.299R + 0.587G + 0.114B); * //// * Cb = (-0.172R - 0.339G + 0.511B) + 128; * //// * Cr = (0.511R - 0.428G - 0.083B) + 128; * //// * regularize * //// * Y = ((64+8+4+1)R + (128+16+4+2)G + (16+8+4+1)B)/256; * //// * Cb = (-(32+8+4)R - (64+32-8-1)G + (128+2+1)B)/256 + 128; * //// * Cr = ((128+2+1)R - (128-16-2)G -(16+4+1)B)/256 + 128; * //// * converter2：rgb-->YUV/YCbCr HDTV * //// * Y = (0.213R + 0.715G + 0.072B); * //// * Cb = (-0.117R - 0.394G + 0.511B) + 128; * //// * Cr = (0.511R - 0.464G - 0.047B) + 128; * //// * regularize * //// * Y = ((32+16+8-1)R + (128+64-8-1)G + (16+2)B)/256; * //// * Cb = (-(32-2)R - (64+32+4+1)G + (128+2+1)B)/256 + 128; * //// * Cr = ((128+2+1)R - (128-8-1)G -(16-4)B)/256 + 128; * //// * converter3：rgb-->YUV/YCbCr PC * //// * Y = 0.299R + 0.587G + 0.114B; * //// * Cb = -0.147R - 0.289G + 0.436B; * //// * Cr = 0.615R - 0.515G - 0.100B; * //// * regularize * //// * Y = ((64+8+4+1)R + (128+16+4+2)G + (16+8+4+1)B)/256; * //// * Cb = (-(32+4+2)R - (64++8+2)G + (128+2+1)B)/256; * //// * Cr = ((128+32-2-1)R - (128+4)G -(16+8+2)B)/256; * //// * Author: Wang Tao * //// * Date: 2007.09.21 * //// * Version Number: 1.0 * //// ************************************end************************************************************** //`timescale 1ns/10psmodule configurable_rgb_to_yuv( dclk, //signal for output data ngreset,//global reset signal href,// valid line signal scontrl,//selective signal r_in, g_in, b_in, y_out, uv_out y_data, u_data, v_data );input dclk;input ngreset, href;input[1:0] scontrl;input[7:0] r_in, g_in, b_in;output[7:0] y_out, uv_out;output[7:0] y_data,u_data,v_data;//-------------------------------------------------------------//// converter1: SDTV ////------------------------------------------------------------////parameter r_in = 0, g_in = 255, b_in = 0;//------------------------------------------------------------//// step1 convert rgb to y_out ////------------------------------------------------------------// //y_outreg[14:0] r64_8;reg[10:0] r4_1;reg[15:0] g128_16;reg[10:0] g4_2;reg[12:0] b16_8;reg[10:0] b4_1;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r64_8 <= 15'h7fff; r4_1 <= 11'h7ff; g128_16 <= 16'hffff; g4_2 <= 11'h7ff; b16_8 <= 13'h1fff; b4_1 <= 11'h7ff; end else begin r64_8 <= {1'b0,r_in,6'b000000} + {4'b0000,r_in,3'b000}; r4_1 <= {1'b0,r_in,2'b00} + {3'b000,r_in}; g128_16 <= {1'b0,g_in,7'b0000000} + {4'b0000,g_in,4'b0000}; g4_2 <= {1'b0,g_in,2'b00} + {2'b00,g_in,1'b0}; b16_8 <= {1'b0,b_in,4'b0000} + {2'b00,b_in,3'b000}; b4_1 <= {1'b0,b_in,2'b00} + {3'b000,b_in}; endreg[15:0] r64_8_4_1;reg[16:0] g128_16_4_2;reg[13:0] b16_8_4_1;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r64_8_4_1 <= 16'hffff; g128_16_4_2 <= 17'h1ffff; b16_8_4_1 <= 14'h3fff; end else begin r64_8_4_1 <= {1'b0,r64_8} + {5'b00000,r4_1}; g128_16_4_2 <= {1'b0,g128_16} + {6'b000000,g4_2}; b16_8_4_1 <= {1'b0,b16_8} + {3'b000,b4_1}; endreg[16:0] r64_b16;reg[16:0] g128_16_4_2d1;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r64_b16 <= 17'h1ffff; g128_16_4_2d1 <= 17'h1ffff; end else begin r64_b16 <= {1'b0,r64_8_4_1} + {3'b000,b16_8_4_1}; g128_16_4_2d1 <= g128_16_4_2; endreg[10:0] rb_g;always @(posedge dclk or negedge ngreset) if(~ngreset) rb_g <= 11'h7ff; else rb_g <= {1'b0,r64_b16[16:7]} + {1'b0,g128_16_4_2d1[16:7]};wire[9:0] y_rgb;reg[7:0] y_temp; //assign y_rgb = (rb_g[7]) ? (rb_g[17:8]+1'b1) : rb_g[17:8]; assign y_rgb = rb_g[10:1];always @(posedge dclk or negedge ngreset) if(~ngreset) y_temp <= 8'h00; else begin if(y_rgb[9:0]>=8'd255) y_temp <= 8'hff; else y_temp <= y_rgb[7:0]; endreg select_uv;always @(posedge dclk or negedge ngreset) if(~ngreset) select_uv <= 1'b0; else if(~href) select_uv <= 1'b0; else select_uv <= ~select_uv;//-----------------------------------------------------------------------------//------------------------------------------------------------//// step2 convert rgb to Cb_out ////------------------------------------------------------------// //Cbreg[13:0] r32_8;reg[9:0] r4;reg[14:0] g64_32;reg[11:0] g8_1;reg[15:0] b128_2;reg[7:0] b1_cb;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r32_8 <= 14'h3fff; r4 <= 10'h3ff; g64_32 <= 15'h7fff; g8_1 <= 12'hfff; b128_2 <= 16'hffff; b1_cb <= 8'hff; end else begin r32_8 <= {1'b0,r_in,5'b00000} + {3'b000,r_in,3'b000}; r4 <= {r_in,2'b00}; g64_32 <= {1'b0,g_in,6'b000000} + {2'b00,g_in,5'b00000}; g8_1 <= {1'b0,g_in,3'b000} + {4'b0000,g_in}; b128_2 <= {1'b0,b_in,7'b0000000} + {7'b0000000,b_in,1'b0}; b1_cb <= b_in; endreg[14:0] r32_8_4;reg[14:0] g64_32_d1;reg[16:0] g8_b128;reg[7:0] b1_d1_cb;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r32_8_4 <= 15'h7fff; g64_32_d1 <= 15'h7fff; g8_b128 <= 17'h1ffff; b1_d1_cb <= 8'hff; end else begin r32_8_4 <= {1'b0,r32_8} + {5'b00000,r4}; g64_32_d1 <= g64_32; g8_b128 <= {5'b00000,g8_1} + {1'b0,b128_2}; b1_d1_cb <= b1_cb; endreg[15:0] r32_g64;reg[9:0] g8_b128_b1_a,g8_b128_b1_b;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r32_g64 <= 16'hffff; //g8_b128_b1 <= 18'h3ffff; g8_b128_b1_a <= 10'h3ff; g8_b128_b1_b <= 10'h3ff; end else begin r32_g64 <= {1'b0,r32_8_4} + {1'b0,g64_32_d1}; //g8_b128_b1 <= {1'b0,g8_b128} + {10'b0000000000,b1_d1_cb}; g8_b128_b1_a <= {1'b0,g8_b128[8:0]} + {2'b00,b1_d1_cb}; g8_b128_b1_b <= {2'b00,g8_b128[16:9]}; endwire[8:0] g8_b128_b1_b2;assign g8_b128_b1_b2 = g8_b128_b1_b[8:0] + g8_b128_b1_a[9]; reg[11:0] rg_b;always @(posedge dclk or negedge ngreset) if(~ngreset) rg_b <= 12'hfff; else begin if(g8_b128_b1_b2 > r32_g64[15:9]) rg_b <= {1'b0,g8_b128_b1_b2,g8_b128_b1_a[8:7]} - {3'b000,r32_g64[15:7]}; else if(g8_b128_b1_b2 < r32_g64[15:9]) rg_b <= {3'b100,r32_g64[15:7]} - {1'b0,g8_b128_b1_b2,g8_b128_b1_a[8:7]}; else begin if(g8_b128_b1_a[8:0] >= r32_g64[8:0]) rg_b <= {1'b0,g8_b128_b1_b2,g8_b128_b1_a[8:7]} - {3'b000,r32_g64[15:7]}; else rg_b <= {3'b100,r32_g64[15:7]} - {1'b0,g8_b128_b1_b2,g8_b128_b1_a[8:7]}; end endwire[10:0] cb_rgb;reg[7:0] cb_temp; //assign cb_rgb = (rg_b[7]) ? (rg_b[18:8]+1'b1) : rg_b[18:8];assign cb_rgb = rg_b[11:1]; always @(posedge dclk or negedge ngreset) if(~ngreset) cb_temp <= 8'h00; else begin if(~cb_rgb[10]) begin if(cb_rgb[9:0]>=8'd127) cb_temp <= 8'hff; else cb_temp <= cb_rgb[7:0] + 8'd128; end else begin if(cb_rgb[9:0]>=8'd128) cb_temp <= 8'h00; else cb_temp <= 8'd128 - cb_rgb[7:0]; end end//-------------------------step2 end-----------------------------// //------------------------------------------------------------//// step3 convert rgb to Cr_out ////------------------------------------------------------------// //Crreg[15:0] r128_2;reg[7:0] r1;reg[12:0] g16_2;reg[12:0] b16_4;reg[15:0] b_g_128;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r128_2 <= 16'hffff; r1 <= 8'hff; g16_2 <= 13'h1fff; b16_4 <= 13'h1fff; b_g_128 <= 16'hffff; end else begin r128_2 <= {1'b0,r_in,7'b0000000} + {7'b0000000,r_in,1'b0}; r1 <= r_in; g16_2 <= {1'b0,g_in,4'b0000} + {4'b0000,g_in,1'b0}; b16_4 <= {1'b0,b_in,4'b0000} + {3'b000,b_in,2'b00}; b_g_128 <= {8'b00000000,b_in} + {1'b0,g_in,7'b0000000}; endreg[16:0] r128_2_1;reg[12:0] g16_2_d1;reg[16:0] b16_g128;always @(posedge dclk or negedge ngreset) if(~ngreset) begin r128_2_1 <= 17'h1ffff; g16_2_d1 <= 13'h1fff; b16_g128 <= 17'h1ffff; end else begin r128_2_1 <= {1'b0,r128_2} + {9'b000000000,r1}; g16_2_d1 <= g16_2; b16_g128 <= {4'b0000,b16_4} + {1'b0,b_g_128}; endreg[9:0] r128_g16_a,r128_g16_b;reg[16:0] b16_g128_b1;always @(posedge dclk or negedge ngreset) if(~ngreset) begin //r128_g16 <= 18'h3ffff; r128_g16_a <= 10'h3ff; r128_g16_b <= 10'h3ff; b16_g128_b1 <= 17'h1ffff; end else begin //r128_g16 <= {1'b0,r128_2_1} + {5'b00000,g16_2_d1}; r128_g16_a <= {1'b0,r128_2_1[8:0]} + {1'b0,g16_2_d1[8:0]}; r128_g16_b <= {2'b00,r128_2_1[16:9]} + {6'b000000,g16_2_d1[12:9]}; b16_g128_b1 <= b16_g128; endwire[8:0] r128_g16_b2;assign r128_g16_b2 = r128_g16_b[8:0] + r128_g16_a[9]; //r128_g16_a[8:0]; reg[11:0] r_gb;always @(posedge dclk or negedge ngreset) if(~ngreset) r_gb <= 12'hfff; else begin if(r128_g16_b2 > b16_g128_b1[16:9]) r_gb <= {1'b0,r128_g16_b2,r128_g16_a[8:7]} - {2'b00,b16_g128_b1[16:7]}; else if(r128_g16_b2 < b16_g128_b1[16:9]) r_gb <= {2'b10,b16_g128_b1[16:7]} - {1'b0,r128_g16_b2,r128_g16_a[8:7]}; else begin if(r128_g16_a[8:0] >= b16_g128_b1[8:0]) r_gb <= {1'b0,r128_g16_b2,r128_g16_a[8:7]} - {2'b00,b16_g128_b1[16:7]}; else r_gb <= {2'b10,b16_g128_b1[16:7]} - {1'b0,r128_g16_b2,r128_g16_a[8:7]}; end end wire[10:0] cr_rgb;reg[7:0] cr_temp; //assign cr_rgb = (r_gb[7]) ? {r_gb[17:8]+1'b1} : r_gb[17:8];assign cr_rgb = r_gb[11:1]; always @(posedge dclk or negedge ngreset) if(~ngreset) cr_temp <= 8'h00; else begin if(~cr_rgb[10]) begin if(cr_rgb[9:0]>=8'd127) cr_temp <= 8'hff; else cr_temp <= cr_rgb[7:0] + 8'd128; end else begin if(cr_rgb[8:0]>=8'd128) cr_temp <= 8'h00; else cr_temp <= 8'd128 - cr_rgb[7:0]; end end//----------------------result----------------------------------------//reg[7:0] y1_out,uv1_out;always @(posedge dclk or negedge ngreset) if(~ngreset) begin y1_out <= 8'h00; uv1_out <= 8'h80; end else begin y1_out <= y_temp; if(select_uv) uv1_out <= cb_temp; else uv1_out <= cr_temp; endreg[7:0] y1_data,u1_data,v1_data;always @(posedge dclk or negedge ngreset) if(~ngreset) begin y1_data <= 8'h00; u1_data <= 8'h80; v1_data <= 8'h80; end else begin y1_data <= y_temp; u1_data <= cb_temp; v1_data <= cr_temp; end //--------------------- converter 1 end ---------------------------//******************************************************************//// converter2: HDTV ////*****************************************************************////------------------------------------------------------------//// step1 convert rgb to y_out ////------------------------------------------------------------// //y_outreg[13:0] r2_1;//32+16reg[10:0] r2_2;//4+1reg[15:0] g2_1;//128+64reg[11:0] g2_2;//8+1reg[12:0] b2_1;//16+2always @(posedge dclk or negedge ngreset) if(~ngreset) begin r2_1 <= 15'h7fff; r2_2 <= 11'h7ff; g2_1 <= 16'hffff; g2_2 <= 12'hfff; b2_1 <= 13'h1fff; end else begin r2_1 <= {1'b0,r_in,5'b00000} + {2'b00,r_in,4'b0000}; r2_2 <= {1'b0,r_in,2'b00} + {3'b000,r_in}; g2_1 <= {1'b0,g_in,7'b0000000} + {2'b00,g_in,6'b000000}; g2_2 <= {1'b0,g_in,3'b000} + {4'b0000,g_in};//- b2_1 <= {1'b0,b_in,4'b0000} + {4'b0000,b_in,1'b0}; endreg[14:0] r2_3;//r2_1+r2_2reg[16:0] gb_1;//g2_1+b2_1always @(posedge dclk or negedge ngreset) if(~ngreset) begin r2_3 <= 15'h7fff; gb_1 <= 17'h1ffff; end else begin r2_3 <= {1'b0,r2_1} + {4'b0000,r2_2}; gb_1 <= {1'b0,g2_1} + {4'b0000,b2_1}; endreg[17:0] rgb_2;//r2_3+gb_1always @(posedge dclk or negedge ngreset) if(~ngreset) rgb_2 <= 18'h3ffff; else rgb_2 <= {1'b0,gb_1} + {3'b000,r2_3}; reg[17:0] r2_d1;always @(posedge dclk or negedge ngreset) if(~ngreset) r2_d1 <= 18'h3ffff; else r2_d1 <= rgb_2 - g2_2;//这种处理无检错，可能会出问题 reg[7:0] y2_temp; wire[9:0] y2_rgb; assign y2_rgb = r2_d1[17:8];always @(posedge dclk or negedge ngreset) if(~ngreset) y2_temp <= 8'h00; else begin if(y2_rgb[9:0]>=8'd255) y2_temp <= 8'hff; else y2_temp <= y2_rgb[7:0]; end//-----------------------------------------------------------------------------//------------------------------------------------------------//// step2 convert rgb to Cb_out ////------------------------------------------------------------// //Cbreg[15:0] b22_1;//(128+1)Breg[9:0] rb2_1;//2R+2Breg[13:0] rg2_1;//32R+32G -reg[10:0] g22_1;//(4+1)G -reg[14:0] g22_2;//64G -always @(posedge dclk or negedge ngreset) if(~ngreset) begin b22_1 <= 16'hffff; rb2_1 <= 10'h3ff; rg2_1 <= 14'h3fff; g22_1 <= 11'hfff; g22_2 <= 15'h7fff; end else begin b22_1 <= {1'b0,b_in,7'b0000000} + {8'b00000000,b_in};//位对齐 rb2_1 <= {1'b0,r_in,1'b0} + {1'b0,b_in,1'b0}; rg2_1 <= {1'b0,r_in,5'b00000} + {1'b0,g_in,5'b00000}; g22_1 <= {1'b0,g_in,2'b00} + {3'b000,g_in}; g22_2 <= {g_in,6'b000000}; endreg[16:0] temp1_d1;//b22_1+rb2_1reg[14:0] temp1_d2;//rg2_1+g22_1always @(posedge dclk or negedge ngreset) if(~ngreset) begin temp1_d1 <= 17'h1ffff; temp1_d2 <= 15'h7fff; end else begin temp1_d1 <= {1'b0,b22_1} + {7'b00000000,rb2_1};//+ temp1_d2 <= {1'b0,rg2_1} + {4'b0000,g22_1};//- endreg[9:0] temp1_d3_a;reg[7:0] temp1_d3_b;always @(posedge dclk or negedge ngreset)⌨️ 快捷键说明
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