config.h

这是WINDRIVER公司所开发的针对freescale公司最新的powerpc系列MPC8560的针对vxworks的bsp。对做powerpc嵌入式的很有用了。

/* Copyright 1984-2004 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01r,30sep04,dtr  Defining RevA board support by default. 256MB DDR.
01q,28jul04,dtr  Mod for revA board, support by default 64MB SDRAM.
01p,22jul04,dtr  Add support for 33MHz clock. Remove orig CPU 29 errata fix.
01o,25may04,dtr  Add INCLUDE_BRANCH_PREDICTION option.
01n,19jan04,dtr  Enable D_CACHE,L2 CACHE and FCC(8560 only) by default.
01m,28oct03,dtr  Support only 32MB for now.
01l,21oct03,dtr  Trim config.h for final release.
01k,02oct03,dtr  Add back in SPE support.
01j,12sep03,dtr  Change some clock defines.
01i,20aug03,dtr  Adding support for TSEC.
01h,14aug03,dtr  Remove undefs for FP and windview.
01g,04aug03,dtr  Modify configuration elements for LBC SDRAM and DDR SDRAM.
01f,29jul03,dtr  Added snoop and disable L2 because of dcbi/dcbst issue.
01e,22jul03,mil  Added flash parameters.
01d,07jul03,mil  Added CPM and SCC.
01c,25jun03,mil  Added prjParams.h for project build.
01b,09oct02,dtr  Added more defines for more complete base for BSP.
01a,03oct02,dtr  Created.
*/
#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/3"
           

/* Define Clock Speed and source  */

#define	FREQ_33_MHZ	 33333333
#define	FREQ_66_MHZ	 66666666
#define	FREQ_100_MHZ	 99999999
#define	FREQ_133_MHZ	133333333
#define	FREQ_266_MHZ	266666666

/* Build for Rev A board by default */
#define ADS_BOARD_REVA

/*
 * This define must be set to the value of the resonant oscillator.
 * For the rev1.8 board default switch settings are for 33MHz
 */

#ifdef ADS_BOARD_REVA
#define	OSCILLATOR_FREQ	FREQ_33_MHZ
#else
#define	OSCILLATOR_FREQ	FREQ_66_MHZ
#endif
/* This value is the 60x bus-assigned SDRAM Refresh Timer PSRT setting */
#define	LSRT_VALUE	0x20

/*
 * This value is the setting for the MPTPR[PTP] Refresh timer prescaler.
 * The value is dependent on the OSCILLATOR_FREQ value.  For other values
 * a conditionally compiled term must be created here for that OSCILLATOR_FREQ
 * value.
 *
 * BRGCLK_DIV_FACTOR
 * Baud Rate Generator division factor - 0 for division by 1
 *					 1 for division by 16
 */

#define	DIV_FACT_1	0
#define	DIV_FACT_16	1

/* Assume Worst case of 333MHz CCB with local bus clk ratio of 4 
 * ie revA board settings */
#define	TPR			0x2000
#define BRGCLK_DIV_FACTOR	DIV_FACT_16

#define M8260_BRGC_DIVISOR	BRGCLK_DIV_FACTOR

#include "configAll.h"

#include "ads85xx.h"

#define WDT_RATE_MIN         (sysTimerClkFreq / (1 << 29))
#define WDT_RATE_MAX         (sysTimerClkFreq / (1 << 21))

#define DEFAULT_BOOT_LINE \
"mottsec(0,0)host:/target/config/ads85xx/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"

/* MMU and CACHE */
#define INCLUDE_MMU_BASIC
#undef  USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE

#define INCLUDE_CACHE_SUPPORT 
#define USER_D_CACHE_ENABLE
#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE  (CACHE_COPYBACK)
#define USER_I_CACHE_ENABLE
#undef  USER_I_CACHE_MODE
#define USER_I_CACHE_MODE (CACHE_COPYBACK)

#define  INCLUDE_L2_CACHE
#undef  INCLUDE_L2_SRAM

/* It is possible a unrecoverable exception will occur 
 * if this is enabled and vxWorks will reboot - rev2.0.2 core */
#undef INCLUDE_L1_ICACHE_PARITY_ERROR_HANDLER

#define INCLUDE_BRANCH_PREDICTION

#if ((defined(INCLUDE_L2_CACHE)) && (defined(INCLUDE_L2_SRAM)))
#define L2_CACHE_SIZE      L2SIZ_128KB
#define L2_SRAM_SIZE       L2SIZ_128KB
#elif ((defined(INCLUDE_L2_CACHE)) && (!defined(INCLUDE_L2_SRAM)))
#define L2_CACHE_SIZE      L2SIZ_256KB
#define L2_SRAM_SIZE       L2SIZ_128KB /* Not Used */
#else
#define L2_SRAM_SIZE       L2SIZ_256KB
#define L2_CACHE_SIZE      L2SIZ_128KB /* Not Used */
#endif

#define L2SRAM_ADDR        0x7FFC0000
#define L2SRAM_WINDOW_SIZE 0x40000 

#ifdef INCLUDE_NFS
/* Default NFS parameters - constants may be changed here, variables
 * may be changed in usrConfig.c at the point where NFS is included.
 */
#define NFS_USER_ID             2001            /* dummy nfs user id */
#define NFS_GROUP_ID            100             /* dummy nfs user group id */
#define NFS_MAXPATH             255             /* max. file path length */
#endif /* INCLUDE_NFS */

/* Disable Support for SPE 64bit registers */
#define INCLUDE_SPE

#define INCLUDE_MOT_TSEC_END
#ifdef INCLUDE_MOT_TSEC_END
#define INCLUDE_PRIMARY_TSEC_END
#define INCLUDE_SECONDARY_TSEC_END    
#define INCLUDE_END                  /* only END-style driver for FCC */
#endif /* INCLUDE_MOT_TSEC_END */


/* INCLUDE_CPM will decides if the serial console will be using
 * the DUART on the 8540, or the SCC on the 8560.  Both should
 * output to the same port.
 */

#ifdef INCLUDE_CPM
#define INCLUDE_SCC_SERIAL
#define INCLUDE_MOTFCCEND
#define INCLUDE_MOT_FCC_END
#else
#define INCLUDE_DUART
#endif

/* Serial channel and TTY */
#undef	NUM_TTY
#if (defined(INCLUDE_DUART) || defined(INCLUDE_SCC_SERIAL))
#  define NUM_TTY 2	       
#else 
#  define NUM_TTY 0
#  undef  INCLUDE_TTY_DEV
#endif  /* INCLUDE_DUART || INCLUDE_SCC_SERIAL */

#ifdef INCLUDE_MOTFCCEND
#ifndef INCLUDE_END
#   define INCLUDE_END                  /* only END-style driver for FCC */
#endif /* INCLUDE_END */

  /* FCC3 Clashes with SCC1 so only include if use SCC2 or no serial */
  /* FCC2 Clashes with SCC2 so only include if use SCC1 or no serial */
#define INCLUDE_PRIMARY_FCC_END /* FCC2 */
#undef INCLUDE_SECONDARY_FCC_END  /* FCC3 */
#endif /* INCLUDE_MOTFCCEND */

/* Optional timestamp support */

#define	INCLUDE_TIMESTAMP
#define	INCLUDE_AUX_CLK

#define EPIC_EX_DFT_SENSE	EPIC_SENSE_EDG
#define EPIC_EX_DFT_POLAR	EPIC_INT_ACT_LOW
#define EPIC_IN_DFT_POLAR	EPIC_INT_ACT_HIGH

/* optional TrueFFS support */
#ifdef  INCLUDE_TFFS
#define INCLUDE_DOSFS		/* dosFs file system */
#define INCLUDE_SHOW_ROUTINES	/* show routines for system facilities*/
#endif  /* INCLUDE_TFFS */

/* clock rates */

#define	SYS_CLK_RATE_MIN	1	/* minimum system clock rate */
#define	SYS_CLK_RATE_MAX	8000	/* maximum system clock rate */
#define	AUX_CLK_RATE_MIN	1	/* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */


/* add on-chip drivers */
#define INCLUDE_PCI               /* include PCI library support */

#ifdef  INCLUDE_PCI
#define INCLUDE_PCI_AUTOCONF
/*
CPU Addr                                         PCI Addr
PCI_LOCAL_MEM_BUS     -------------------------- PCI_MSTR_MEM_BUS
                      -                        - 
                      -                        -
PCI_LOCAL_MEM_BUS +   -------------------------- PCI_MSTR_MEM_BUS +
PCI_LOCAL_MEM_SIZE    -                        - PCI_MSTR_MEM_SIZE
                      -                        - 
                      -                        ----- PCI Bridge   
                      -                        -     configuration regs
                      -                        - 
CPU_PCI_MEM_ADRS      -------------------------- PCI_MEM_ADRS
                      -                        - 
                      -                        - 
CPU_PCI_MEMIO_ADRS    -------------------------- PCI_MEMIO_ADRS
                      -                        - 
                      -                        - 
CPU_PCI_IO_ADRS       -------------------------- PCI_IO_ADRS
                      -                        -
                      -                        -
CPU_PCI_IO_ADRS +     -------------------------- PCI_IO_ADRS +
CPU_PCI_IO_SIZE       -                        - PCI_IO_SIZE
                      -                        -
                      -                        -
                      ----PCI Bridge           -
                      -------------------------- 4GBytes 
*/



/* for custom sysPciAutoConfig.c */


/* PCI based addresses */
#define PCI_MEM_ADRS         0x80000000 
#define PCI_MEM_SIZE         0x01000000   /* 16MB */
#define PCI_MEMIO_ADRS       0x90000000
#define PCI_MEMIO_SIZE       0x01000000   /* 16MB */
#define PCI_IO_ADRS          0xa0000000 
#define PCI_IO_SIZE          0x01000000   /* 16MB */

#define PCI_MEM_SIZE_MASK  PCI_ATTR_WS_16M
#define PCI_MEMIO_SIZE_MASK PCI_ATTR_WS_16M

/* CPU based addresses */
#define CPU_PCI_MEM_ADRS          0x80000000
#define CPU_PCI_MEM_SIZE          PCI_MEM_SIZE 
#define CPU_PCI_MEMIO_ADRS        0x90000000
#define CPU_PCI_MEMIO_SIZE        PCI_MEMIO_SIZE 
#define CPU_PCI_IO_ADRS           0xa0000000
#define CPU_PCI_IO_SIZE           PCI_IO_SIZE

/* CPU from PCI bus */
#define PCI_MSTR_MEM_BUS           0x00000000
#define PCI_MSTR_MEM_SIZE          0x40000000 /* 1G */
#define PCI_BRIDGE_PIMMR_BASE_ADRS  0x50000000

/* CPU Address that is visible from PCI */
#define PCI_LOCAL_MEM_BUS         0x00000000
#define PCI_LOCAL_MEM_SIZE        PCI_MSTR_MEM_SIZE
#define PCI_LOCAL_MEM_SIZE_MASK   PCI_ATTR_WS_1G

#ifndef PCI_CFG_TYPE
#   ifdef INCLUDE_PCI_AUTOCONF
#      define PCI_CFG_TYPE PCI_CFG_AUTO
#   else
#      define PCI_CFG_TYPE PCI_CFG_FORCE
#   endif /* INCLUDE_PCI_AUTOCONF */
#endif /* PCI_CFG_TYPE */

#endif /* INCLUDE_PCI */

#ifdef INCLUDE_PCI

#undef INCLUDE_FEI_END

#ifdef INCLUDE_FEI_END
#define INCLUDE_PRIMARY_FEI_END
#undef INCLUDE_SECONDARY_FEI_END
#define INCLUDE_END                  
#endif /* INCLUDE_FEI_END */

#endif

/* remove unnecessary drivers */

#undef INCLUDE_SM_NET
#undef INCLUDE_SM_SEQ_ADD

/* flash for boot params */
#define INCLUDE_FLASH
#ifdef  INCLUDE_FLASH
#  define SYS_FLASH_TYPE        FLASH_28F640J3A    /* flash device type */
#ifdef ADS_PROTOTYPE
#  define FLASH_WIDTH           2
#else /* ADS_PROTOTYPE */
#  define FLASH_WIDTH           4
#endif /* ADS_PROTOTYPE */
#  define FLASH_CHIP_WIDTH      2
#  define FLASH_WIDTH_SPECIAL_2
#  define FLASH_SEGMENT_SIZE    0x20000

#  define FLASH_ADRS            (0xff800000 + 0x700000 - FLASH_SEGMENT_SIZE)
#  define FLASH_SIZE            FLASH_SEGMENT_SIZE
#  define FLASH_SIZE_WRITEABLE  FLASH_SEGMENT_SIZE
#  define NV_RAM_SIZE           FLASH_SEGMENT_SIZE
#  undef  FLASH_NO_OVERLAY
#  undef  NV_BOOT_OFFSET
#  define NV_BOOT_OFFSET        FLASH_SEGMENT_SIZE - 0x200
#else  /* INCLUDE_FLASH */
#  define NV_RAM_SIZE           NONE
#endif  /* INCLUDE_FLASH */

#ifdef ADS_PROTOTYPE
#ifdef VISION_VXWORKS
#define FLASH_BASE_ADRS                 0x3f800000
#else 
#define FLASH_BASE_ADRS                 0xff800000
#endif
#define FLASH_ADRS_MASK                 0xff800000
#define FLASH_WINDOW_SIZE               0x00800000 
#else /* ADS_PROTOTYPE */
#ifdef VISION_VXWORKS
#define FLASH_BASE_ADRS                 0x3f000000
#else 
#define FLASH_BASE_ADRS                 0xff000000
#endif
#define FLASH_ADRS_MASK                 0xff000000
#define FLASH_WINDOW_SIZE               0x01000000 
#endif /* ADS_PROTOTYPE */

/* Memory addresses */

/* NOTE this should match the LAWAR SIZE in romInit for the chosen SDRAM */
#define LOCAL_MEM_SIZE          0x10000000      /* 256 Mbyte memory available */
#define LOCAL_MEM_LOCAL_ADRS    0x00000000      /* Base of RAM */
 
#define INCLUDE_LBC_SDRAM
#define INCLUDE_DDR_SDRAM
#define INCLUDE_SECONDARY_DRAM
/* NOTE this should match the LAWAR SIZE in romInit for the chosen SDRAM */
#define LOCAL_MEM_SIZE2          0x4000000      /* 64 Mbyte memory available */
#define LOCAL_MEM_LOCAL_ADRS2    0x10000000      /* Base of RAM */
#define LBC_SDRAM_LOCAL_SIZE_MASK  0xfc000000
#define LBC_SDRAM_LOCAL_ADRS       LOCAL_MEM_LOCAL_ADRS2
#define LBC_SDRAM_LOCAL_SIZE       LOCAL_MEM_SIZE2
#define DDR_SDRAM_LOCAL_ADRS       LOCAL_MEM_LOCAL_ADRS
#define DDR_SDRAM_LOCAL_SIZE       LOCAL_MEM_SIZE
#define DDR_SDRAM_LOCAL_ADRS_END   (DDR_SDRAM_LOCAL_ADRS + DDR_SDRAM_LOCAL_SIZE)

/*
 * Default power management mode - selected via vxPowerModeSet() in
 * sysHwInit().
 */

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

#define INCLUDE_CTORS_DTORS

/* Using software FP support. Athough task based 32 bit HW_FP is allowed 
 * no optimised libraries are available. The kernel doesn't execute any hw 
 * fp instructions */
#undef  INCLUDE_HW_FP
#undef  INCLUDE_PPC_FPU
#define INCLUDE_SW_FP

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
 * in config.h, MakeSkel, Makefile, and Makefile.*
 * All definitions for these constants must be identical.
 */
 
#define ROM_TEXT_ADRS 0xFFF00100

#define RAM_HIGH_ADRS 0xd00000
#define RAM_LOW_ADRS  0x10000

#define ROM_BASE_ADRS 0xFFF00000
#define ROM_SIZE      0x00100000

#define USER_RESERVED_MEM 0x000000

#ifdef __cplusplus
    }
#endif /* __cplusplus */

#endif  /* INCconfigh */

#if defined(PRJ_BUILD)
    #include "prjParams.h"
#endif /* PRJ_BUILD */