target.nr

这是WINDRIVER公司所开发的针对freescale公司最新的powerpc系列MPC8560的针对vxworks的bsp。对做powerpc嵌入式的很有用了。

'\" t
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.\" ads85xx/target.nr - Motorola MPC85XXADS target specific documentation
.\"
.\" Copyright 1984-2004 Wind River Systems, Inc.
.\"
.\" modification history
.\" --------------------
.\" 01c,21nov04,dtr  Support now only for revA board. DDR now 256MB default.
.\" 01b,21jul04,dtr  Include info for revA board.
.\" 01a,16oct03,dtr  Created
.\"
.\"
.TH "ads85xx" T "Motorola MPC85XXADS" "Rev: 20 Oct 2003" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MPC85XXADS"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks for the ads8540/8560 BSP. 


.SH "BOOT ROMS"
.CS
No VxWorks Boot ROM is provided with this BSP release. Nevertheless VxWorks
boot code is working if downloaded into the on board Flash.
This is can be done using the UBOOT. See Motorola documentation on the UBOOT
to see how to flash bootrom into the top 1MB of flash.
.CE

.SS "Programming bootrom using WIND POWER IDE"

.CS
Assumption here you can connect to the target using WIND POWER(WP) ICE/IDE.
The ads85xx.vsh file in this bsp contains the register settings for the ICE.
This file can be played in the command window by right click and selecting 
play. Doing an 'in' at the BKM> prompt then performs the required board 
initialisation to enable the flash programmer to work.
Also make sure Flash program enable jumper J1 is set to 2-3 closed.
The flash programmer is in the tool menu of the WP IDE.
Select the file tab and convert your bootrom.hex supplied in the BSP to a 
binary. Start Address = 0 End Address = 0xffffffff. Tick box to add to flash 
list and click on convert. After complete modify start address of this 
converted file to be FFF00000 and tick enabled. 
Now click on Configuration Tab, confirm INTEL  2 * 16bit 28F640J3x devices 
selected. Confirm flash address is at 0xff000000. Now select only addresses 
fff00000 and click on erase/program. You should be able to verify that a 
bootrom exists at FFF00100. A reference to Wind river copyright should be 
there. 

If this fails check list is:
1) Confirm switches and jumpers on board 
2) Close window go back to command window verify you can read/write to 
address 0x100. 
3) Also verify the register file has executed by doing 'dr BR0' in command window and verifying BR0 = ff001801 or verify all the registers enabled with values below.

Some other possible issues: 
1) ICE Firmware revision vn1.2a or later.
2) WIND POWER IDE 1.2

.CE


.SH "FEATURES"

.SH "Supported Features (PILOT board revisions)"

.SH "ADS8540"

.CS
System Clock
Aux clock
Watchdog
L2Cache
L2SRAM
EPIC
DUART
TSEC
PCI
TFFS
128MB DDR SDRAM
64MB LBC SDRAM
.CE

.SH "ADS8560"
.CS
System clock
Aux clock
Watchdog
L2 Cache
L2 SRAM
EPIC
CPM interrupt controller
SCC1/2
TSEC 
PCI 
TFFS
128MB  DDR SDRAM
64MB  LBC SDRAM

.CE

.SS "Feature Interactions"
None known

.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and board
hardware elements.

.SS "Devices"
The chip drivers included are:

.SS "Generic:"
    cfiscs.c - flash memory driver
    m85xxTimer.c - timer driver
    miiLib.c - Media Independent Interface library
    mot85xxPci.c - On-chip PCI Bridge library/interrupt handler.
    sysEpic.c - On chip interrupt controller
    motTsecEnd.c - TSEC ethernet controller
.SS "ADS8540:"
    ns16553Sio.c - serial driver
.SS "ADS8560:"
    m8260Sio.c - serial driver
    m85xxCpmIntrCtl.c - CPM interrupt controller driver

The 8560 BSP configures both SCC1 and SCC2 as UART devices. 
SCC1 is used as a console device.

.SS "Memory Maps"
.LP
The following table describes the ads85xx default memory map:
.TS E
allbox expand;
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
Start	Size	End	Access to
_
0x0000_0000	256MB	0x0FFF_FFFF	DDR SDRAM
0x1000_0000	64MB	0x13FF_FFFF	LBC SDRAM
0xFE00_0000	1MB	0xFE0F_FFFF	Configuaration Control Registers
0xFF00_0000	16MB	0xFFFF_FFFF	Flash SIMM
.TE

.LP
The following table describes the default VxWorks macros which
are used to address memory
.TS E
expand;
lf3 lf3 lf3
l l l .
.ne 6
.sp .5
Macro Name	Macro Definition	Description
_
LOCAL_MEM_LOCAL_ADRS	0x0000_0000	Base of RAM
RAM_LOW_ADRST	LOCAL_MEM_LOCAL_ADRS + 0x0001_0000	T{VxWorks image loaded here. Stack grows down from this address.T}
RAM_HIGH_ADRS	T{
LOCAL_MEM_LOCAL_ADRS + 0x00d0_0000
T}	T{VxWorks bootrom loaded here.T}
LOCAL_MEM_SIZE	0100_0000	Default 16 MBytes of RAM
ROM_BASE_ADRS	0xFFF0_0000	Base address of ROM on PILOT rev
ROM_TEXT_ADRS	T{
ROM_BASE_ADRS + 0x100
T}	T{Text must start after vector table T}
ROM_WARM_ADRS	T{
ROM_TEXT_ADRS + 8
T}	Warm Reboot Entry Address
ROM_SIZE	0x0010_0000	Default 1 MByte of ROM on PILOT rev (see ROM considerations)
.TE
.sp

.SS "Shared Memory"
NA

.SS "PCI Support"
.LP
The standard mapping for PCI is described in config.h of this BSP and uses 
outbound translation to access. This means PCI space usage is configurable by
the user in config.h. 

.SS "Serial Configuration"
SCC1 and SCC2 are configured as UART devices with 8 data bits, 1 stop
bit, hardware handshaking, and parity disabled. 

.SS "SCSI Configuration"
There is no SCSI interface on this board.

.SS "Network Configuration"
TSEC is configured as an Ethernet port

.SS "VME Access"
NA

.SS "PCI Access"
PCI interface is available.

.SS "Boot Devices"
mottsec

.SS "Boot Methods"
.CS
Ethernet
Load vxWorks image via WINDPOWER ICE.
.CE

.SS "ROM Considerations for PILOT board revision"
The actual size of Flash memory on this board is 16MB

The BSP was tested with both compressed and uncompressed boot roms
programmed at ROM_BASE_ADRS. If there is not enough space for the
bootrom image or a vxWorks standalone image is required to be in
ROM, this can be achieved by placing a stub that jumps to start of
flash memory. This requires either a compiler which can
provide 2 text segments or manually programming the stub and the
main image at different locations without overwriting each other.


.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information that the user needs
to know about the BSP.

.SS "Delivered Objects"

.SS "Make Targets"
.CS
bootrom.bin
vxWorks
vxWorks.st
bootrom_uncmp.bin
bootrom.hex
bootrom_uncmp.hex
.CE

.SS "Special Routines"
None


See also "Known Problems" below.

.SS "Documentation Errata"

.SS "Known Problems"
.CS
See Rev2.0 Silicon.
See RevA Board.
.CE

.SS "Tested Configuration"

.SS "Switch Settings - Rev Pilot - no longer supported"

.TS E
allbox expand;
lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3
l l l l l l l l l l l l .
.ne 12
.sp .5
SW Pin->	1	2	3	4	5	6	7	8	9	10
-
1	OFF	OFF	OFF	OFF	OFF	OFF
2	OFF 	OFF 	OFF	OFF 	OFF	OFF
3	OFF	OFF	OFF	OFF	OFF	OFF
4	ON	ON	ON	ON	ON	ON	OFF	OFF
5	ON	ON	OFF 	OFF	OFF	OFF	OFF	OFF	OFF	OFF
6	ON	OFF	ON	ON 	OFF	ON	OFF	OFF  
7	OFF	OFF	OFF	OFF	OFF	OFF	OFF	OFF
8	OFF
9	ON	ON
10 	ON	OFF	OFF	OFF 	OFF	OFF	ON	ON
11 ADS8540	OFF	ON	OFF	OFF	OFF	OFF	OFF	ON 
11 ADS8560	OFF	OFF	OFF	OFF	OFF	OFF	OFF	ON 
12	OFF	ON	ON	OFF	OFF	ON	ON	ON	ON	ON 
13	OFF	ON	ON	ON            
14	ON	ON	ON 	ON
15	ON  	OFF 	OFF 	OFF	ON	OFF
16	ON  	ON  	ON  	ON 
17	OFF 	ON  	ON  	ON  	ON  	OFF 	ON  	ON 
18	OFF
19	OFF
20	ON	OFF 	OFF 	ON  	OFF	OFF
21	OFF
22	OFF 	OFF  	ON  	OFF
23	ON  	OFF 	ON  	OFF 	OFF 	ON 
24	OFF
25	ON  	OFF 	OFF 	OFF 	OFF 	ON
26	OFF
27	OFF
28	ON
29	ON  	ON  	OFF 	ON

.TE

.SS "Switch Settings - Rev A"

.TS E
allbox expand;
lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3 lf3
l l l l l l l l l l l l .
.ne 12
.sp .5
SW Pin->	1	2	3	4	5	6	7	8	9	10
-
1	OFF	OFF	OFF	OFF	OFF	OFF
2	OFF 	OFF 	OFF	OFF 	OFF	OFF
3	OFF	OFF	OFF	OFF	OFF	OFF
4	ON	ON	ON	ON	ON	ON	OFF	OFF
5       OFF     OFF     ON      ON
6	ON	ON	OFF 	OFF	OFF	OFF	OFF	OFF	OFF	OFF
7	OFF	ON	OFF	ON 	ON	OFF	OFF	OFF  
8	OFF	OFF	OFF	OFF	OFF	OFF	OFF	OFF
9	OFF
10 	OFF	OFF	OFF	OFF 	OFF	OFF	ON	ON
11      OFF	ON
12 ADS8540	OFF	ON	OFF	ON	ON	OFF	ON	ON 
12 ADS8560	OFF	OFF	OFF	ON	ON	OFF	ON	ON 
13      ON	OFF	ON	OFF	OFF	ON
14	OFF	ON	ON	OFF	OFF	ON	ON	ON	ON	ON       
15	ON	ON	ON 	ON
16	OFF  	OFF 	OFF 	OFF	ON	OFF
17	ON  	ON  	ON  	ON 
18	OFF 	ON  	ON  	ON  	ON  	OFF 	ON  	OFF
19	OFF
20	OFF 
21	ON	OFF 	OFF 	ON  	OFF	OFF
22	OFF 	ON  	ON  	OFF
23	OFF
24	OFF
25	OFF  	ON 	ON  	ON 	ON 	OFF 
26	OFF
27	OFF
28	ON
29	ON  	ON  	OFF 	ON
30	ON	OFF	ON	ON
.TE

.SS "Jumper Settings - Rev A"

J6 - 2-3 to enable programming flash
J22 - 2-3
J24 - 1-2 MII
J25 - 1-2 MII
J33 - 1-2 MII
J37 - 1-2 MII
J38 - 1-2 Enable GVDD
J49 - 1-2 Enable ATM (unsupported)
J50 - connect
J51 - connect
J52 - 1-2 Enable ATM (unsupported)

.SS Rev 2.0 silicon

On Pilot board Switch 11 pin 7 should be ON for rev2 silicon and off for 
rev 1. Rev 2 silicon comes with CPU errata #29 which requires an OS patch.
You should ensure patch for SPR 99776 is installed if you enable the 
instruction MMU.

.SS Pilot Board

The pilot board is no longer supported.

.SS Rev A Board
Rev A is now the default build.
The default switch settings in MPC8560ADS_RevA_QuickRefGuide Rev1.15 which 
are specified above. The CCB is set to 333MHz and the Core Freq is 833MHz. 
The LBC SDRAM is using 83MHz. All other frequencies within chip/board spec 
shoud work also. 

.SH "SEE ALSO"
.tG "Getting Started,"


.pG "Configuration," 

.pG "Architecture Appendix"

.SH "BIBLIOGRAPHY"
.CS
MPC8560_Users_Manual.pdf
MPC8540_Users_Manual.pdf
MPC8560ADS_Users_Manual.pdf
MPC8560ADSPilot1_QuickRefGuide.pdf
MPC8560ADS_RevA_QuickRefGuide.pdf
e500_core_users_manual.pdf

See Freescale's web site for all the documentation related to the hardware.
.CE

http://www.freescale.com/