m8260sio.c

这是WINDRIVER公司所开发的针对freescale公司最新的powerpc系列MPC8560的针对vxworks的bsp。对做powerpc嵌入式的很有用了。

    while ((*pBRGC) & M8260_BRGC_RST);

    m8260SioIoctl (pSccChan, SIO_BAUD_SET, pSccChan->baudRate);

    /* set up the RECEIVE buffer descriptors */

    /* buffer status/control */
    M8260_SCC_16_WR((pSccChan->pBdBase + 
                     M8260_SCC_RCV_BD_OFF + 
                     M8260_SCC_BD_STAT_OFF), 0xB000);
    CACHE_PIPE_FLUSH ();

    /* buffer length */
    M8260_SCC_16_WR((pSccChan->pBdBase + 
                     M8260_SCC_RCV_BD_OFF + 
                     M8260_SCC_BD_LEN_OFF), 0x0001);
    CACHE_PIPE_FLUSH ();

    /* buffer address */

    M8260_SCC_32_WR((pSccChan->pBdBase + 
                     M8260_SCC_RCV_BD_OFF + 
                     M8260_SCC_BD_ADDR_OFF), pSccChan->rcvBufferAddr);

    /* set the SCC parameter ram field RBASE */

    *pSccChan->pRBASE = (UINT16)((UINT32)pSccChan->pBdBase & 0xffff);

    /* set up the TRANSMIT buffer descriptors */

    /* 
     * buffer status/control;
     * not ready, Wrap, Bit Clear-to-send_report, Interrupt 
     */

    M8260_SCC_16_WR((pSccChan->pBdBase + 
                     M8260_SCC_TX_BD_OFF + 
                     M8260_SCC_BD_STAT_OFF), 0x3800);

    /* buffer length */

    M8260_SCC_16_WR((pSccChan->pBdBase + 
                     M8260_SCC_TX_BD_OFF + 
                     M8260_SCC_BD_LEN_OFF), 0x0001);

    /* buffer address */

    M8260_SCC_32_WR((pSccChan->pBdBase + 
                     M8260_SCC_TX_BD_OFF + 
                     M8260_SCC_BD_ADDR_OFF), pSccChan->txBufferAddr);

    /* set the SCC parameter ram field TBASE */

    * pSccChan->pTBASE =  ((UINT16)((UINT32)pSccChan->pBdBase & 0xffff) + 0x08);

    /* disable transmit and receive interrupts */

    * pSCCM &= ~(M8260_SCC_UART_SCCX_RX | M8260_SCC_UART_SCCX_TX);

    /* program the three SCC mode registers: gsmrl, gsmrh, and psmr */

    /* 
     * Protocol Specific Mode Register for SCC
     * Normal CTS, 1 stop bit, 8 data bits 
     */

    * pPSMR   = M8260_SCC_UART_PSMR_FLC  | M8260_SCC_UART_PSMR_CL_8BIT;


    /* 
     * General Serial Mode Register for SCC, high word
     * xmit fifo is 1 byte, receive fifo 8 bits 
     */

    * pGSMR_H = M8260_SCC_GSMRH_RFW      | M8260_SCC_GSMRH_TFL;

    /* 
     * General Serial Mode Register for SCC, low word
     * set SCC attributes to standard UART mode, disable xmit and rcv
     */

    * pGSMR_L = (M8260_SCC_GSMRL_RDCR_X16 | 
		 M8260_SCC_GSMRL_TDCR_X16 | 
		 M8260_SCC_GSMRL_UART) 
		 & ~
		 (M8260_SCC_GSMRL_ENT | M8260_SCC_GSMRL_ENR);

    /* initialize parameter RAM area for this SCC */

    * pRFCR = 0x18;	/* supervisor data access */

    * pTFCR = 0x18;	/* supervisor data access */

    * pMRBLR = 1;

    /* initialize some unused parameters in SCC parameter RAM */

    * pMAX_IDL = 0x0;
    * pBRKCR = 0x0001;
    * pPAREC = 0x0;
    * pFRMEC = 0x0;
    * pNOSEC = 0x0;
    * pBRKEC = 0x0;
    * pUADDR1 = 0x0;
    * pUADDR2 = 0x0;
    * pTOSEQ = 0x0;
    * pCHARACTER1 = 0x8000;
    * pCHARACTER2 = 0x8000;
    * pCHARACTER3 = 0x8000;
    * pCHARACTER4 = 0x8000;
    * pCHARACTER5 = 0x8000;
    * pCHARACTER6 = 0x8000;
    * pCHARACTER7 = 0x8000;
    * pCHARACTER8 = 0x8000;
    * pRCCM = 0x0C0FF;

    CACHE_PIPE_FLUSH ();

   /* wait until the CP is clear */
    ix = 0;
    do
        {
        M8260_SCC_32_RD((M8260_CPCR (immrVal)), cpcrVal);

        if (ix++ == M8260_CPCR_LATENCY)
            break;
        } while (cpcrVal & M8260_CPCR_FLG) ;

    if (ix >= M8260_CPCR_LATENCY)
        {

        /* what to do, other than log an error? */

        }

    /* Tell CP to initialize tx and rx parameters for SCC */

    cpcrVal = (M8260_CPCR_OP (M8260_CPCR_RT_INIT)
               | M8260_CPCR_SBC (M8260_CPCR_SBC_SCC1 | (scc * 0x1))
               | M8260_CPCR_PAGE (M8260_CPCR_PAGE_SCC1 | (scc * 0x1))
               | M8260_CPCR_MCN (M8260_CPCR_MCN_ETH)
               | M8260_CPCR_FLG);

    M8260_SCC_32_WR (M8260_CPCR (immrVal), cpcrVal);

    CACHE_PIPE_FLUSH ();

    /* wait until the CP is clear */

    ix = 0;
    do
        {
        M8260_SCC_32_RD((M8260_CPCR (immrVal)), cpcrVal);

        if (ix++ == M8260_CPCR_LATENCY)
            break;
        } while (cpcrVal & M8260_CPCR_FLG) ;

    if (ix >= M8260_CPCR_LATENCY)
        {

        /* what to do, other than log an error? */

        }

    CACHE_PIPE_FLUSH ();

    /* lastly, enable the transmitter and receiver  */

    * pGSMR_L |= (M8260_SCC_GSMRL_ENT | M8260_SCC_GSMRL_ENR);

    CACHE_PIPE_FLUSH ();

    intUnlock (oldlevel);			/* UNLOCK INTERRUPTS */
    }

/*******************************************************************************
*
* m8260SioIoctl - special device control
*
* Allows the caller to get and set the buad rate; to get and set the mode;
* and to get the allowable modes.
*
* RETURNS: OK on success, EIO on device error, ENOSYS on unsupported
*          request.
*
*/

LOCAL STATUS m8260SioIoctl
    (
    M8260_SCC_CHAN *	pSccChan,	/* device to control */
    int			request,	/* request code */
    int			arg		/* some argument */
    )
    {
    int 	oldlevel;
    STATUS 	status = OK;
    UINT8       sccNum = pSccChan->sccNum;      /* holder for the fcc number */
    UINT8       scc = sccNum - 1;            	/* a convenience */
    UINT32      immrVal = pSccChan->immrVal;    /* holder for the immr value */
    int         baudRate;
    int         baud;

    VUINT32 *pBRGC = (VUINT32 *) (immrVal + M8260_BRGC_BASE + 
			        (scc * M8260_BRGC_OFFSET_NEXT_BRGC));


    VUINT16 *pSCCM = (VUINT16 *) (immrVal + M8260_SCC_BASE + M8260_SCCM_OFFSET +
		      	        (scc * M8260_SCC_OFFSET_NEXT_SCC));

    switch (request)
	{
	case SIO_BAUD_SET:
	    if (arg >=  300 && arg <= 38400)     /* could go higher... */
                {
                baudRate = (baudRateGenClk + (8 * arg)) / (16 * arg);

                if (--baudRate > 0xfff)
                    baud = (M8260_BRGC_CD_MASK &
                   (((baudRate + 8) / 16) << M8260_BRGC_CD_SHIFT)) |\
                    M8260_BRGC_EN | M8260_BRGC_DIVISOR ;
                else
                    baud = ( M8260_BRGC_CD_MASK &
                        (baudRate << 1)) | M8260_BRGC_EN;

                *pBRGC = baud;

                pSccChan->baudRate = arg;
                }
            else
	        status = EIO;
	    break;
    
	case SIO_BAUD_GET:
	    * (int *) arg = pSccChan->baudRate;
	    break;

	case SIO_MODE_SET:
            if (!((int) arg == SIO_MODE_POLL || (int) arg == SIO_MODE_INT))
                {
                status = EIO;
                break;
                }

            /* lock interrupt  */

            oldlevel = intLock();

            /* initialize channel on first MODE_SET */

            if (!pSccChan->channelMode)
                m8260SioResetChannel(pSccChan);

            if (arg == SIO_MODE_INT)
		{

		/* enable SCC interrupts at the SIU Interrupt Controller */

		if (scc == 0) 
		    {
                    m85xxCpmIntEnable(INUM_CPM_SCC1);
		    }
		else if (scc == 1) 
		    {
                    m85xxCpmIntEnable(INUM_CPM_SCC2);
		    }

		/* enable receive and transmit interrupts at the scc */

		* pSCCM |= (M8260_SCC_UART_SCCX_RX | M8260_SCC_UART_SCCX_TX);

		CACHE_PIPE_FLUSH ();

		}
            else
		{

		/* disable transmit and receive interrupts */

		* pSCCM &= ~(M8260_SCC_UART_SCCX_RX | M8260_SCC_UART_SCCX_TX);

		CACHE_PIPE_FLUSH ();

		/* mask off this SCC's interrupt */ 

		if (scc == 0) 
		  m85xxCpmIntDisable(INUM_CPM_SCC1);
		/*  m8260IntDisable(INUM_SCC1); */
		else if (scc == 1) 
		  m85xxCpmIntDisable(INUM_CPM_SCC2);
/*                     m8260IntDisable(INUM_SCC2); */
		CACHE_PIPE_FLUSH ();

                }

            pSccChan->channelMode = arg;

            intUnlock(oldlevel);

            break;

        case SIO_MODE_GET:
            * (int *) arg = pSccChan->channelMode;
	    break;

        case SIO_AVAIL_MODES_GET:
            *(int *)arg = SIO_MODE_INT | SIO_MODE_POLL;
	    break;

	default:
	    status = ENOSYS;
	}

    return (status);
    }

/*******************************************************************************
*
* m8260SioInt - handle an SCC interrupt
*
* This routine is called to handle SCC interrupts.
*
* RETURNS: NA
*/

void m8260SioInt
    (
    M8260_SCC_CHAN *pSccChan
    )
    {
    char		outChar;
    VUINT16              bdStatus;      /* holder for the BD status */
    UINT8       sccNum = pSccChan->sccNum;      /* holder for the fcc number */
    UINT8       scc = sccNum - 1;            	/* a convenience */
    UINT32      immrVal = pSccChan->immrVal;    /* holder for the immr value */

    VUINT16 *pSCCE = (VUINT16 *) (immrVal + M8260_SCC_BASE + M8260_SCCE_OFFSET +
		      	        (scc * M8260_SCC_OFFSET_NEXT_SCC));

    CACHE_PIPE_FLUSH ();

    /* check for a receive event */

    if (* pSCCE & M8260_SCC_UART_SCCX_RX )
	{

	/*
	 * clear receive event bit by setting the bit in the event register.
	 * This also clears the bit in SIPNR
	 */

        * pSCCE = M8260_SCC_UART_SCCX_RX; 
	CACHE_PIPE_FLUSH ();

	/* 
	 * as long as there is a character: