📄 ads85xx.h
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#define M85XX_MCMR(base) (CAST(VUINT32 *)((base) + 0x5078))#define M85XX_MRTPR(base) (CAST(VUINT32 *)((base) + 0x5084))#define MRTPR_PTP_MASK 0xff000000#define MRTPR_PTP_WRITE(x) ( (x << 24) & MRTPR_PTP_MASK)#define M85XX_MDR(base) (CAST(VUINT32 *)((base) + 0x5088))#define M85XX_LSDMR(base) (CAST(VUINT32 *)((base) + 0x5094))#define LSDMR_RFEN 0x40000000 /* Refresh Enable *//* LSDMR OP - 000 Normal operation * - 001 Auto Refresh (Initialization) * - 010 Self Refresh * - 011 Mode Register Write (Initialization) * - 100 Precharge Bank * - 101 Precharge all banks (Initialization) * - 110 Activate Bank * - 111 Read/Write without valid transfer */ #define LSDMR_OP_MASK 0x38000000#define LSDMR_OP_SHIFT(x) ((x << 27) & LSDMR_OP_MASK)/* Bank Select Multiplexed address line - 000 lines 12:13 * - 001 13:14 * - 010 14:15 * - 011 15:16 * - 100 16:17 * - 101 17:18 * - 110 18:19 * - 111 19:20 */#define LSDMR_BSMA_MASK 0x00E00000#define LSDMR_BSMA_SHIFT(x) ((x << 23) & LSDMR_BSMA_MASK)/* RFCR Refresh recovery 000 - reserved * 001->110 - 3->8 clocks * 111 - 16 clocks */#define LSDMR_RFCR_MASK 0x00038000#define LSDMR_RFCR_SHIFT(x) ((x << 15) & LSDMR_RFCR_MASK)/* Incomplete LSDMR definitions */#define M85XX_LURT(base) (CAST(VUINT32 *)((base) + 0x50A0))#define M85XX_LSRT(base) (CAST(VUINT32 *)((base) + 0x50A4))#define M85XX_LTESR(base) (CAST(VUINT32 *)((base) + 0x50B0))#define M85XX_LTEDR(base) (CAST(VUINT32 *)((base) + 0x50B4))#define M85XX_LTEIR(base) (CAST(VUINT32 *)((base) + 0x50B8))#define M85XX_LTEATR(base) (CAST(VUINT32 *)((base) + 0x50BC))#define M85XX_LTEAR(base) (CAST(VUINT32 *)((base) + 0x50C0))/* LBC Clock Configuration */#define M85XX_LBCR(base) (CAST(VUINT32 *)((base) + 0x50D0))#define M85XX_LCRR(base) (CAST(VUINT32 *)((base) + 0x50D4))/* ECM Registers */#define ECM_OFFSET 0x1000#define ECMBA (CCSBAR | ECM_OFFSET)/* Offsets for DDR registers */#define DDR_OFFSET 0x2000#define DDRBA (CCSBAR | DDR_OFFSET)#define CS0_BNDS 0x000#define CS1_BNDS 0x008#define CS2_BNDS 0x010#define CS3_BNDS 0x018#define CS0_CONFIG 0x080#define CS1_CONFIG 0x084#define CS2_CONFIG 0x088#define CS3_CONFIG 0x08C#define TIMING_CFG_1 0x108#define TIMING_CFG_2 0x10C#define DDR_SDRAM_CFG 0x110#define DDR_SDRAM_MODE_CFG 0x118#define DDR_SDRAM_INTERVAL 0x124#define DDR_DATA_ERR_INJECT_HI 0xe00#define DDR_DATA_ERR_INJECT_LO 0xe04#define DDR_ECC_ERR_INJECT 0xe08#define DDR_CAPTURE_DATA_HI 0xe20#define DDR_CAPTURE_DATA_LO 0xe24#define DDR_CAPTURE_ECC 0xe28#define DDR_ERR_DETECT 0xe40#define DDR_ERR_DISABLE 0xe44#define DDR_ERR_INT_EN 0xe48#define DDR_CAPTURE_ATTRIBUTES 0xe4c#define DDR_CAPTURE_ADDRESS 0xe50#define DDR_ERR_SBE 0xe58/*PIC Base Address */#define PIC_OFFSET 0x40000#define PCIBA (CCSBAR | PIC_OFFSET)/* CPU type in the PVR */#define CPU_TYPE_8260 0xAAAA /* value for PPC8260 */#define CPU_TYPE_8266 0xBBBB /* value for PPC8266 */#define CPU_REV_A1_MASK_NUM 0x0010 /* revision mask num */#define HIP4_ID 0x80810000 /* device ID via PVR */#define HIP4_MASK 0xFFFF0000 /* mask upper word *//* * Maximum number of SCC channels to configure as SIOs. Note that this * assumes sequential usage of SCCs.*/#define MAX_SCC_SIO_CHANS 2#define M85XX_CPM_SICR(base) (CAST(VUINT16 *)((base) + 0x90c00))#define M85XX_CPM_SIVEC(base) (CAST(VUINT8 *)((base) + 0x90c04))#define M85XX_CPM_SIPNR_H(base) (CAST(VUINT32 *)((base) + 0x90c08))#define M85XX_CPM_SIPNR_L(base) (CAST(VUINT32 *)((base) + 0x90c0c))#define M85XX_CPM_SCPRR_H(base) (CAST(VUINT32 *)((base) + 0x90c14))#define M85XX_CPM_SCPRR_L(base) (CAST(VUINT32 *)((base) + 0x90c18))#define M85XX_CPM_SIMR_H(base) (CAST(VUINT32 *)((base) + 0x90c1c))#define M85XX_CPM_SIMR_L(base) (CAST(VUINT32 *)((base) + 0x90c20))#define M85XX_CPM_SIEXR(base) (CAST(VUINT32 *)((base) + 0x90c24))#define M85XX_CPM_SCCR(base) (CAST(VUINT32 *)((base) + 0x90c80))/* Global Function Registers *//* PORPLL used to detect clocking ratio for CCB/CPM for serial devices *//* Plat Ratio not working on board need to test!!!!*/ #define M85XX_PORPLLSR(base) (CAST(VUINT32 *)((base) + 0xE0000))#define M85XX_PORPLLSR_E500_RATIO_MASK 0x003f0000#define M85XX_PORPLLSR_PLAT_RATIO_MASK 0x0000003e#define M85XX_PORPLLSR_E500_RATIO(base) ((*M85XX_PORPLLSR(base) & M85XX_PORPLLSR_E500_RATIO_MASK)>>16)#define M85XX_PORPLLSR_PLAT_RATIO(base) ((*M85XX_PORPLLSR(base) & M85XX_PORPLLSR_PLAT_RATIO_MASK)>>1)#define M85XX_DDRDLLCR(base) (CAST(VUINT32 *)((base) + 0xE0E10))#define M85XX_LBCDLLSR(base) (CAST(VUINT32 *)((base) + 0xE0E20))#define M85XX_DEVDISR(base) (CAST(VUINT32 *)((base) + 0xE0070))#define M85XX_DEVDISR_DDR 0x00010000#define M85XX_PVR(base) (CAST(VUINT32 *)((base) + 0xE00A0))#define M85XX_SVR(base) (CAST(VUINT32 *)((base) + 0xE00A4))#define _PPC_BUCSR_FI 0x200 /* Invalidate branch cache */#define _PPC_BUCSR_E 0x1 /* Enable branch prediction *//* Port A, B, C and D Defines */#define PA31 (0x00000001)#define PA30 (0x00000002)#define PA29 (0x00000004)#define PA28 (0x00000008)#define PA27 (0x00000010)#define PA26 (0x00000020)#define PA25 (0x00000040)#define PA24 (0x00000080)#define PA23 (0x00000100)#define PA22 (0x00000200)#define PA21 (0x00000400)#define PA20 (0x00000800)#define PA19 (0x00001000)#define PA18 (0x00002000)#define PA17 (0x00004000)#define PA16 (0x00008000)#define PA15 (0x00010000)#define PA14 (0x00020000)#define PA13 (0x00040000)#define PA12 (0x00080000)#define PA11 (0x00100000)#define PA10 (0x00200000)#define PA9 (0x00400000)#define PA8 (0x00800000)#define PA7 (0x01000000)#define PA6 (0x02000000)#define PA5 (0x04000000)#define PA4 (0x08000000)#define PA3 (0x10000000)#define PA2 (0x20000000)#define PA1 (0x40000000)#define PA0 (0x80000000)#define PB31 (0x00000001)#define PB30 (0x00000002)#define PB29 (0x00000004)#define PB28 (0x00000008)#define PB27 (0x00000010)#define PB26 (0x00000020)#define PB25 (0x00000040)#define PB24 (0x00000080)#define PB23 (0x00000100)#define PB22 (0x00000200)#define PB21 (0x00000400)#define PB20 (0x00000800)#define PB19 (0x00001000)#define PB18 (0x00002000)#define PB17 (0x00004000)#define PB16 (0x00008000)#define PB15 (0x00010000)#define PB14 (0x00020000)#define PB13 (0x00040000)#define PB12 (0x00080000)#define PB11 (0x00100000)#define PB10 (0x00200000)#define PB9 (0x00400000)#define PB8 (0x00800000)#define PB7 (0x01000000)#define PB6 (0x02000000)#define PB5 (0x04000000)#define PB4 (0x08000000)#define PC31 (0x00000001)#define PC30 (0x00000002)#define PC29 (0x00000004)#define PC28 (0x00000008)#define PC27 (0x00000010)#define PC26 (0x00000020)#define PC25 (0x00000040)#define PC24 (0x00000080)#define PC23 (0x00000100)#define PC22 (0x00000200)#define PC21 (0x00000400)#define PC20 (0x00000800)#define PC19 (0x00001000)#define PC18 (0x00002000)#define PC17 (0x00004000)#define PC16 (0x00008000)#define PC15 (0x00010000)#define PC14 (0x00020000)#define PC13 (0x00040000)#define PC12 (0x00080000)#define PC11 (0x00100000)#define PC10 (0x00200000)#define PC9 (0x00400000)#define PC8 (0x00800000)#define PC7 (0x01000000)#define PC6 (0x02000000)#define PC5 (0x04000000)#define PC4 (0x08000000)#define PC3 (0x10000000)#define PC2 (0x20000000)#define PC1 (0x40000000)#define PC0 (0x80000000)#define PD31 (0x00000001)#define PD30 (0x00000002)#define PD29 (0x00000004)#define PD28 (0x00000008)#define PD27 (0x00000010)#define PD26 (0x00000020)#define PD25 (0x00000040)#define PD24 (0x00000080)#define PD23 (0x00000100)#define PD22 (0x00000200)#define PD21 (0x00000400)#define PD20 (0x00000800)#define PD19 (0x00001000)#define PD18 (0x00002000)#define PD17 (0x00004000)#define PD16 (0x00008000)#define PD15 (0x00010000)#define PD14 (0x00020000)#define PD13 (0x00040000)#define PD12 (0x00080000)#define PD11 (0x00100000)#define PD10 (0x00200000)#define PD9 (0x00400000)#define PD8 (0x00800000)#define PD7 (0x01000000)#define PD6 (0x02000000)#define PD5 (0x04000000)#define PD4 (0x08000000)#ifdef __cplusplus }#endif /* __cplusplus */#endif /* INCads85xxh */⌨️ 快捷键说明
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