sysepic.c

这是WINDRIVER公司所开发的针对freescale公司最新的powerpc系列MPC8560的针对vxworks的bsp。对做powerpc嵌入式的很有用了。

*/

UINT32 epicCisr0Get (void)
    {
    volatile unsigned long val;

    val = *(volatile unsigned long *) (CCSBAR | 0x41330);
    return val;
    }

/***************************************************************************
*
* epicCisr1Get - get critical interrupt summary
*
*/
UINT32 epicCisr1Get (void)
    {
    volatile unsigned long val;

    val = *(volatile unsigned long *) (CCSBAR | 0x41340);
    return val;
    }

/*******************************************************************************
*
* sysEpicCrtIntHandler
*
*/

LOCAL void  sysEpicCrtIntHandler (void)
    {
    int oldkey;

    volatile unsigned long extSumm;
    volatile unsigned long intSumm;
    int i;

    while (((extSumm = (epicCisr0Get() & 0xfff)) != 0) ||
           ((intSumm = epicCisr1Get()) != 0))
        {
        /* service external first */
        for (i = 0; i < 12; i++)
            {
            if (((extSumm >> i) & 0x1) == 0x1)
                {
                /* CPU_INT_UNLOCK (_PPC_MSR_CE); */
                sysEpicIntHandlerExec (11 - i);
                /* CPU_INT_LOCK (&oldkey); */
                }
            }

        /* service internal */
        for (i = 0; i < 32; i++)
            {
            if (((intSumm >> i) & 0x1) == 0x1)
                {
                /* CPU_INT_UNLOCK (_PPC_MSR_CE); */
                sysEpicIntHandlerExec (EPIC_VEC_IN_IRQ0 + 31 - i);
                /* CPU_INT_LOCK (&oldkey); */
                }
            }

        }
    }
#endif  /* INCLUDE_EPIC_CRT_INTR */

/*******************************************************************************
*
* epicCurTaskPrioSet - set the priority of the current task.
*
* NOTES
*
* epicCurTaskPrioSet sets the priority of the Processor Current Task
* Priority register to the value of the prioNum parameter.  This function
* should be called after sysEpicInit() to lower the priority of the processor
* current task. Note that valid priority values are 0 through 15 (15 being
* the highest priority)
*
* NOMANUAL
* 
* RETURNS: previous priority of the task.
*/

int epicCurTaskPrioSet
    (
    int prioNum
    )
    {
    ULONG oldPrio;

    if ((prioNum < EPIC_PRIORITY_MIN) || (prioNum > EPIC_PRIORITY_MAX))
        {
        return ((int) EPIC_INV_PRIO_ERROR);
	}

    oldPrio = sysEpicRegRead (EPIC_CTASK_PRI_REG);

    sysEpicRegWrite (EPIC_CTASK_PRI_REG, prioNum);

    return (oldPrio);
    }

/*******************************************************************************
*
* epicIntEnable - enable an EPIC interrupt, given its IVPR
*
* This function clears the mask bit of an external, an internal or
* a Timer register to enable the interrupt.
*
* <srcAddr> is the address offset of the Vector Priority register  
*
* NOMANUAL
* 
* RETURNS: OK or an error code if the IVPR passed in was invalid.
*/

LOCAL int epicIntEnable
    (
    ULONG 	srcAddr
    )
    {
    ULONG 	srcVal;
    int 	errCode;
  
    errCode = epicSrcAddrCheck (srcAddr);

    if (errCode == EPIC_INV_INTER_SOURCE)
        {
        return (errCode);
        }

    srcVal = sysEpicRegRead (srcAddr);

    switch (errCode)
        {
        case EPIC_EX_INTERRUPT:
            srcVal &= ~(EPIC_EIVPR_INTR_MSK);   /* clear the mask bit */
        break;

        case EPIC_IN_INTERRUPT:
            srcVal &= ~(EPIC_IIVPR_INTR_MSK);   /* clear the mask bit */
        break;

        case EPIC_GT_INTERRUPT:
            srcVal &= ~(EPIC_GTVPR_INTR_MSK);   /* clear the mask bit */
        break;

        case EPIC_MSG_INTERRUPT:
            srcVal &= ~(EPIC_MIVPR_INTR_MSK);   /* clear the mask bit */
        break;

        case EPIC_IPI_INTERRUPT:
            srcVal &= ~(EPIC_IPIVPR_INTR_MSK);  /* clear the mask bit */
        break;

        default:
            return (ERROR);
        }

    sysEpicRegWrite (srcAddr, srcVal);

    return OK;

    }

/*******************************************************************************
*
* epicIntDisable - disable an EPIC interrupt, given its IVPR
*
* This function sets the mask bit of an external, an internal,
* a timer, a message, or an IPI register to disable the interrupt.
* <srcAddr> is the address offset of the Vector Priority register.
*
* NOMANUAL
* 
* RETURNS: OK or an error code if the IVPR passed in was invalid.
*/
               
LOCAL int epicIntDisable
    (
    ULONG 	srcAddr
    )
    {
    ULONG 	srcVal;
    int 	errCode;
  
    errCode = epicSrcAddrCheck (srcAddr);

    if (errCode == EPIC_INV_INTER_SOURCE)
        {
        return (errCode);
        }

    srcVal = sysEpicRegRead (srcAddr);

    switch (errCode)
        {
        case EPIC_EX_INTERRUPT:
            srcVal |= EPIC_EIVPR_INTR_MSK;	/* set the mask bit */
        break;

        case EPIC_IN_INTERRUPT:
            srcVal |= EPIC_IIVPR_INTR_MSK;	/* set the mask bit */
        break;

        case EPIC_GT_INTERRUPT:
            srcVal |= EPIC_GTVPR_INTR_MSK;	/* set the mask bit */
        break;

        case EPIC_MSG_INTERRUPT:
            srcVal |= EPIC_MIVPR_INTR_MSK;	/* set the mask bit */
        break;

        case EPIC_IPI_INTERRUPT:
            srcVal |= EPIC_IPIVPR_INTR_MSK;	/* set the mask bit */
        break;

        default:
            return (ERROR);
        }

    sysEpicRegWrite (srcAddr, srcVal);

    return OK;
    }

#ifdef INCLUDE_EPIC_CRT_INTR
/*******************************************************************************
*
*/
LOCAL int epicCrtIntSet
    (
    ULONG 	srcAddr
    )
    {
    ULONG 	srcVal;
    int 	errCode = EPIC_EX_INTERRUPT;    /* same bits for all types */
  
    srcVal = sysEpicRegRead (srcAddr);

    switch (errCode)
        {
        case EPIC_EX_INTERRUPT:
            srcVal |= EPIC_EIDR_CRIT_INT;       /* set critical bit */
        break;

        case EPIC_IN_INTERRUPT:
            srcVal |= EPIC_IIDR_CRIT_INT;       /* set critical bit */
        break;

        case EPIC_GT_INTERRUPT:
            return (ERROR);                     /* not supported */
        break;

        case EPIC_MSG_INTERRUPT:
            srcVal |= EPIC_MIDR_CRIT_INT;       /* set critical bit */
        break;

        case EPIC_IPI_INTERRUPT:
            return (ERROR);                     /* not supported */
        break;

        default:
            return (ERROR);
        }

    sysEpicRegWrite (srcAddr, srcVal);

    return OK;
    }

/*******************************************************************************
*
*/
LOCAL int epicCrtIntUnset
    (
    ULONG 	srcAddr
    )
    {
    ULONG 	srcVal;
    int 	errCode = EPIC_EX_INTERRUPT;    /* same bits for all types */
  
    srcVal = sysEpicRegRead (srcAddr);

    switch (errCode)
        {
        case EPIC_EX_INTERRUPT:
            srcVal &= ~(EPIC_EIDR_CRIT_INT);    /* set critical bit */
        break;

        case EPIC_IN_INTERRUPT:
            srcVal &= ~(EPIC_IIDR_CRIT_INT);    /* set critical bit */
        break;

        case EPIC_GT_INTERRUPT:
            return (ERROR);                     /* not supported */
        break;

        case EPIC_MSG_INTERRUPT:
            srcVal &= ~(EPIC_MIDR_CRIT_INT);    /* set critical bit */
        break;

        case EPIC_IPI_INTERRUPT:
            return (ERROR);                     /* not supported */
        break;

        default:
            return (ERROR);
        }

    sysEpicRegWrite (srcAddr, srcVal);

    return OK;
    }

/*******************************************************************************
*
*/
LOCAL int epicCrtIntGet
    (
    ULONG 	srcAddr
    )
    {
    ULONG 	srcVal;
    int 	errCode = EPIC_EX_INTERRUPT;    /* same bits for all types */
  
    srcVal = sysEpicRegRead (srcAddr);

    switch (errCode)
        {
        case EPIC_EX_INTERRUPT:
            srcVal = (srcVal >> 30) & 1;
        break;
        }

    return srcVal;
}

/*******************************************************************************
*
*/
int  sysEpicCrtIntSet
    (
    int vector
    )
    {

    if ((vector < 0)  || (vector >= EPIC_MAX_ALL_IRQS))
        return (ERROR);

    /* enable critical bit on EPIC */

    return epicCrtIntSet ( epicGetDestRegAdrs (vector) );
    }

/*******************************************************************************
*
*/
int  sysEpicCrtIntUnset
    (
    int vector
    )
    {

    if ((vector < 0)  || (vector >= EPIC_MAX_ALL_IRQS))
        return (ERROR);

    /* disable critical bit on EPIC */

    return epicCrtIntUnset ( epicGetDestRegAdrs (vector) );
    }

/*******************************************************************************
*
*/
int  sysEpicCrtIntGet
    (
    int vector
    )
    {

    if ((vector < 0)  || (vector >= EPIC_MAX_ALL_IRQS))
        return (ERROR);

    /* obtain critical bit on EPIC */

    return epicCrtIntGet ( epicGetDestRegAdrs (vector) );
    }
#endif  /* INCLUDE_EPIC_CRT_INTR */

/*******************************************************************************
*
* epicIntAck - read the IACK register and return vector
* 
* NOTES
*
* epicIntAck reads the Interrupt acknowldge register and return
* the vector number of the highest pending interrupt.
*
* NOMANUAL
* 
* RETURNS: the vector number of the highest priority pending interrupt.
*/

int epicIntAck(void)
    {
    int eumbVal;

    eumbVal = sysEpicRegRead (EPIC_INT_ACK_REG);
    WRS_ASM ("eieio");
    return eumbVal;

    }

/*******************************************************************************
*
* epic EOI 0 signal end of interrupt on the EPIC
*
* NOTES
*
* epicEOI writes 0x0 to the EOI register to signal end of interrupt.
* This function is usually called after an interrupt routine is served.
*
* NOMANUAL
* 
* RETURNS: N/A
*/

void epicEOI(void)
    {
    sysEpicRegWrite (EPIC_EOI_REG, 0x0);
    }

/*******************************************************************************
*
* epicGetVecRegAdrs - translate a vector to vector reg address
*
* NOMANUAL
*
* RETURNS: the vector register address of the corresponding vector type
*/

ULONG epicGetVecRegAdrs
    (
    int vector
    )
    {
    if ((vector < EPIC_VEC_EXT_IRQ0) || (vector >= EPIC_VEC_CTRL_EXT))
        return ((ULONG) ERROR);