📄 task5_5402.c.svn-base
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/****************************************************************************
文件名称:task5_5402.c
版本号: 1.0
日期: 2006-06-29
说明: 与5402进行控制。
修改历史:--
****************************************************************************/
#include "includes.h"
#include "os_tasks.h"
#include "globe.h"
#include "watchdog.h"
#include "netif.h"
#include "ne2kif.h"
#include "tcpip.h"
#include "memp.h"
#include "hpi.h"
#include "dsp2arm.h"
#include "sys_UART.h"
#include "fpga_config.h"
#define TASK5_DEBUG 1
#define CONFIG_5402 1
/*
#if UART_DEBUG == 1
UART_Printf("\n");
#endif
*/
void disable_hpi_isr(void);
void istall_hpi_isr(void);
void Eint2_isr(void);
OS_STK Task5Stack[TASK5_STACKSIZE];
unsigned short g_hpi_type;
OS_EVENT *g_sem_5402; //this semaphore is uesd to make the task5 and the Eint2_isr synchro.
/*********************task5 start*************************/
void Task5(void *pdata)
{
#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
OS_CPU_SR cpu_sr;
#endif
#if TASK5_DEBUG == 1
unsigned int CCD_data_count = 0;
unsigned int CCD_preData_count = 0;
unsigned int CCD_reset_count = 0;
unsigned int CCD_int_err = 0;
unsigned short test1 = 0, test2 = 0;
#endif
INT8U err;
int config_state;
pdata = pdata; //just aviod warning
#if UART_DEBUG == 1
UART_Printf("Task5 begin.\n");
#endif
reset_dsp:
//config FPGA
OS_ENTER_CRITICAL(); //sdy0607017 maybe need
#if UART_DEBUG == 1
UART_Printf("Config FPGA begin.\n");
#endif
config_state = FConfig();
if(config_state != FOK)
{
#if UART_DEBUG == 1
UART_Printf("Config FPGA failure.\n");
#endif
goto reset_dsp;
}
OS_EXIT_CRITICAL();
#if CONFIG_5402 == 1
//config 5402
rPDATF = rPDATF & 0xfff7;
OSTimeDly(20);
rPDATF = rPDATF | 0x0008;
OSTimeDly(2);
#endif
//install the hpi interrupt isr
istall_hpi_isr();
OS_ENTER_CRITICAL();
//HintClear();
HInit();
#if TASK5_DEBUG == 1
for(test1 = 0x80; test1<0x4000; test1++)
{
HWriteS(test1, 0x0);
}
for(test1 = 0x80; test1<0x4000; test1++)
{
HReadS(test1, &test2);
if(test2 != 0)
{
#if UART_DEBUG == 1
UART_Printf("5402 writing test error.\n");
#endif
}
}
#endif
#if UART_DEBUG == 1
UART_Printf("Config 5402 begin.\n");
#endif
#if CONFIG_5402 == 1
HBootLoad();
#endif
#if UART_DEBUG == 1
UART_Printf("Config 5402 over.\n");
#endif
#if TASK5_DEBUG == 1
HReadS(0x1000,&test1);
HReadS(0x1001,&test2);
HReadS(0x007f,&test1);
#endif
OS_EXIT_CRITICAL();
//shake hands with 5402 and get CCD data
while(1)
{
OSSemPend(g_sem_5402, (INT16U)0, &err);
#if UART_DEBUG == 1
UART_Printf("5402 interrupt, type %d.\n", g_hpi_type);
#endif
switch(g_hpi_type)
{
case SHK_INITI_SUCC:
HWriteS(DSP_INT_TYPEF, SHK_CCD_BEGIN);
OSTimeDly(100);
Hint();
break;
case SHK_FPGA_ERR:
#if TASK5_DEBUG == 1
CCD_reset_count++;
#endif
#if UART_DEBUG == 1
UART_Printf("FPGA error, reset.\n");
#endif
#if CONFIG_5402 == 1
disable_hpi_isr();
rPDATF = rPDATF & 0xfff7;
OSTimeDly(20);
rPDATF = rPDATF | 0x0008;
OSTimeDly(2);
#endif
goto reset_dsp;
break;
case SHK_DATA_OK:
#if TASK5_DEBUG == 1
CCD_data_count++;
#endif
read_band_value();
read_raw_data(); //sdy060710
break;
case SHK_SDRAM_FULL:
break;
case SHK_PRE_DATA:
#if TASK5_DEBUG == 1
CCD_preData_count++;
#endif
read_pre_data();
break;
case SHK_INT_ERR:
#if TASK5_DEBUG == 1
CCD_int_err++;
#endif
break;
default:
;
}
}
}
/*********************task5 end*************************/
//interrupt from 5402 hpi
void Eint2_isr(void)
{
OS_SEM_DATA sem_data;
HReadS(DSP_INT_TYPET, &g_hpi_type);
OSSemQuery(g_sem_5402, &sem_data);
if(sem_data.OSCnt == 0)
{
OSSemPost(g_sem_5402);
}
rI_ISPC = BIT_EINT2;
HintClear();
}
//install the hpi_int isr
void istall_hpi_isr(void)
{
rINTMSK |= BIT_EINT2; //close the Eint2 interrupt
rI_ISPC = BIT_EINT2; //changeif
pISR_EINT2= (U32)Eint2_isr;
g_sem_5402 = OSSemCreate(0);
rINTMSK &= ~BIT_EINT2;
}
//disable the hpi_int isr
void disable_hpi_isr(void)
{
rINTMSK |= BIT_EINT2; //close the Eint2 interrupt
}
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