task4_watchdog.c.svn-base

lwip协议在arm7+uCos系统上的移植

/****************************************************************************
  文件名称：task4_Watchdog.c
  版本号：	1.0
  日期：	2006-06-21
  说明：	监控系统中的各个部分，不正常时复位。

  修改历史：--
****************************************************************************/

#include "includes.h"
#include "os_tasks.h"
#include "globe.h"
#include "watchdog.h"

#include "netif.h"
#include "ne2kif.h"
#include "tcpip.h"
#include "memp.h"


OS_STK Task4Stack[TASK4_STACKSIZE];

//OS_EVENT *g_sem_NetReset;		//this semaphore is uesd to Rest the rtl8019
static unsigned int g_ui_watch;
static unsigned int g_watch_mask;

void Wat_NetReset(void);

/*********************task4 start*************************/
void Task4(void *pdata)
{
	#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
    	OS_CPU_SR  cpu_sr;
	#endif
	
	#if WAT_DEBUG == 1
		unsigned int Net_Reset_Tim = 0;
	#endif
	
	int TimCoe;
	unsigned int temp;

	pdata = pdata;	//just aviod warning
	
	g_ui_watch = 0;
	g_watch_mask = WAT_BIT_GLOBAL;
	
	while(1)
	{
		for(TimCoe=1; TimCoe <= WAT_MAX_TIP; TimCoe++)
		{ 
			OSTimeDly(WAT_TIP_TIME);
			
			//net reset
			if(TimCoe%NET_COE == 0)
			{
				OS_ENTER_CRITICAL();
				temp = (g_ui_watch | g_watch_mask) & WAT_BIT_NET;	//sdy060630
				OS_EXIT_CRITICAL();
				
				if(temp == 0)
				{
					Wat_NetReset();
					#if WAT_DEBUG == 1
						Net_Reset_Tim++;
					#endif
				}
				else
				{
					OS_ENTER_CRITICAL();
					g_ui_watch &= ~WAT_BIT_NET;
					OS_EXIT_CRITICAL();
				}
			}
			//other reset
		}
		
	}	  
}
/*********************task4 end*************************/
//feed
void Wat_Feed(unsigned int type)
{
	#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
    	OS_CPU_SR  cpu_sr;
	#endif
	OS_ENTER_CRITICAL();
	g_ui_watch |= type;
	OS_EXIT_CRITICAL();
}
//enable watchdog
void Wat_Enable(unsigned int type)
{
	#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
    	OS_CPU_SR  cpu_sr;
	#endif

	OS_ENTER_CRITICAL();
	g_watch_mask &= ~type;
	OS_EXIT_CRITICAL();
}
//disable watchdog
void Wat_Disable(unsigned int type)
{
	#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
    	OS_CPU_SR  cpu_sr;
	#endif

	OS_ENTER_CRITICAL();
	g_watch_mask |= type;
	OS_EXIT_CRITICAL();
}

/*********************Reset*************************/
//Wat_NetReset
void Wat_NetReset(void)
{
	char temp;
	
	rINTMSK |= BIT_EINT1;
	
	outb(0x22, NE_CR);
	
	//write and read 0x1f to reset the nic
	outb(0, NE_RESET);
	temp = inb(NE_RESET); 
	//delay at least 10ms
	OSTimeDly(5);	//sdy060612	

	//in PAGE0
	outb(CMD_PAGE0 | CMD_NODMA | CMD_STOP, NE_CR);
	//OSTimeDly(10);	//sdy060612
	/* FIFO threshold = 8 bytes, normal operation, 8-bit byte write DMA, BOS=0 */
	outb(DCR_LS | DCR_FIFO8, NE_DCR);
	
	outb(0, NE_RBCR0);
	outb(0, NE_RBCR1);
	
	//Place the SNIC in LOOPBACK mode 1 or 2 (Transmit Configuration Register e 02H or 04H)
	outb(TCR_LOOP_INT, NE_TCR);

	outb(XMIT_START >> 8, NE_TPSR);
	outb(RECV_START >> 8, NE_PSTART);
	outb(RECV_START >> 8, NE_BNRY);
	outb(RECV_STOP >> 8, NE_PSTOP);
	//in PAGE1
	outb(CMD_PAGE1 | CMD_NODMA | CMD_STOP, NE_CR);
	outb(RECV_START >> 8, NE_CURR); //nothingbn 06_03_24

 // Set physical address here.(not use 93c46)
	outb(locnode.mac[0], NE_PAR0);
	outb(locnode.mac[1], NE_PAR1);
	outb(locnode.mac[2], NE_PAR2);
	outb(locnode.mac[3], NE_PAR3);
	outb(locnode.mac[4], NE_PAR4);
	outb(locnode.mac[5], NE_PAR5);
	
	//nothingbn 06_03_21
	//Clear multicast filters.(reject all multicast)
	outb(0, NE_MAR0); outb(0, NE_MAR1);
	outb(0, NE_MAR2); outb(0, NE_MAR3);
	outb(0, NE_MAR4); outb(0, NE_MAR5);
	outb(0, NE_MAR6); outb(0, NE_MAR7);
	
	//select PAGE0 and start the nic
	outb(CMD_PAGE0 | CMD_NODMA | CMD_RUN, NE_CR);
	//set Interrupt mask reg
	outb(ISR_OVW | ISR_TXE | ISR_PTX | ISR_PRX, NE_IMR);
	
	outb(TCR_LOOP_NONE, NE_TCR);
	//clear all interrupts
	outb(0xff, NE_ISR);
	
	rINTMSK &= ~BIT_EINT1;
}