st79_clk.h

st公司新出的一款8位单片机st79的lib库

  CLK_FLAG_BYPASS_POS         = (u8)0x08, /*!< CLK Flag position */
  CLK_FLAG_PLLREF_POS         = (u8)0x04, /*!< CLK Flag position */
  CLK_FLAG_SWIF_POS           = (u8)0x08, /*!< CLK Flag position */
  CLK_FLAG_SWBSY_POS          = (u8)0x01, /*!< CLK Flag position */
  CLK_FLAG_CSSD_POS           = (u8)0x08, /*!< CLK Flag position */
  CLK_FLAG_AUX_POS            = (u8)0x02, /*!< CLK Flag position */
  CLK_FLAG_CCOBSY_POS         = (u8)0x40, /*!< CLK Flag position */
  CLK_FLAG_CCORDY_POS         = (u8)0x20  /*!< CLK Flag position */
} CLK_ClockFlagPosition_TypeDef;

/** CLK Clock Source */
typedef enum {
  CLK_SYSCLKSOURCE_HSI    = (u8)0xE1, /*!< Clock Source HSI. */
  CLK_SYSCLKSOURCE_LSI    = (u8)0xD2, /*!< Clock Source LSI. */
  CLK_SYSCLKSOURCE_HSE    = (u8)0xB4, /*!< Clock Source HSE. */
  CLK_SYSCLKSOURCE_PLLCLK = (u8)0x78  /*!< Clock Source PLL. */
} CLK_ClockSources_TypeDef;

/** CLK switck interrupt and Security system */
typedef enum {
  CLK_IT_SWIE   = (u8)0x01, /*!< Clock switch interrupt */
  CLK_IT_CSSDIE = (u8)0x02  /*!< Clock security system detection interrupt */
} CLK_ClockInterruptSource_TypeDef;

/** Clock Oscillator Used */
typedef enum {
  CLK_HSE_USER_EXT   = (u8)0x00, /*!< High Speed Oscilletor, External. */
  CLK_HSE_OSC_QUARTZ = (u8)0x01  /*!< High Speed Oscilletor, Quartz. */
} CLK_HSEOscilletorUsed_TypeDef;

/** CLK Clock Divisor. */
/* Warning:
   0xxxxxx = HSI divider
   1xxxxxx = CPU divider
   Other bits correspond to the divider's bits mapping
*/
typedef enum {
  CLK_HSI_DIV1   = (u8)0x00, /*!< High speed internal clock prescaler: 1 */
  CLK_HSI_DIV2   = (u8)0x08, /*!< High speed internal clock prescaler: 2 */
  CLK_HSI_DIV4   = (u8)0x10, /*!< High speed internal clock prescaler: 4 */
  CLK_HSI_DIV8   = (u8)0x18, /*!< High speed internal clock prescaler: 8 */
  CLK_CPU_DIV1   = (u8)0x80, /*!< CPU clock division factors 1 */
  CLK_CPU_DIV2   = (u8)0x81, /*!< CPU clock division factors 2 */
  CLK_CPU_DIV4   = (u8)0x82, /*!< CPU clock division factors 4 */
  CLK_CPU_DIV8   = (u8)0x83, /*!< CPU clock division factors 8 */
  CLK_CPU_DIV16  = (u8)0x84, /*!< CPU clock division factors 16 */
  CLK_CPU_DIV32  = (u8)0x85, /*!< CPU clock division factors 32 */
  CLK_CPU_DIV64  = (u8)0x86, /*!< CPU clock division factors 64 */
  CLK_CPU_DIV128 = (u8)0x87  /*!< CPU clock division factors 128 */
} CLK_ClockFrequencyDivisor_TypeDef;

/** CLK PLL Spead Control */
typedef enum {
  CLK_PLLCENTERSPREADTYPE = (u8)0x20, /*!< PLL, Center Spead. */
  CLK_PLLDOWNSPREADTYPE   = (u8)0x00  /*!< PLL, Down Spead. */
} CLK_SpreadControl_TypeDef;

/** CLK PLL SSCG Control */
typedef enum {
  CLK_PLL_SSCG_ON  = (u8)0x10, /*!< PLL, SSCG mode ON. */
  CLK_PLL_SSCG_OFF = (u8)0x00  /*!< PLL, SSCG mode OFF. */
} CLK_SSCGClockMode_TypeDef;

/** CLK PLL Bypass Control */
typedef enum {
  CLK_PLL_REFFREQ = (u8)0x08, /*!< PLL, Reference Frequency. */
  CLK_PLL_DIV3    = (u8)0x00  /*!< PLL, frequency divide by three. */
} CLK_ClockBypass_TypeDef;

/** CLK PLL Reference Control */
typedef enum {
  CLK_PLL_HSE = (u8)0x04, /*!< HSE PLL reference frequency. */
  CLK_PLL_HSI = (u8)0x00  /*!< HSI PLL reference frequency. */
} CLK_Reference_TypeDef;

typedef u8 CLK_ClockSources; /*!< System Clock Sources */

typedef CLK_ClockSources CLK_ClockFrequencyDivisor; /*!< Clock Frequency Divisor */

typedef CLK_ClockSources CLK_InterruptPendingClear; /*!< Interrupt Pending bit Clear */

/**
  * @}
  */

/* Exported constants --------------------------------------------------------*/

/** @addtogroup CLK_Exported_Constants
  * @{
  */

#define HSI_VALUE   ((u32)16000000) /*!< Typical Value of the HSI in Hz */
#define LSI_VALUE   ((u32)128000)   /*!< Typical Value of the LSI in Hz */
#define CLK_TIMEOUT ((u16)0x491)    /*!< Timeout for the clock switch operation. */

/**
  * @}
  */

/* Private macros ------------------------------------------------------------*/

/**
  * @brief Macros used by the assert function in order to check the different functions parameters.
  * @addtogroup CLK_Private_Macros
  * @{
  */

#define IS_CLK_SWITCHMODE_OK(MODE) ((MODE == CLK_SWITCHMODE_MANUAL) || (MODE == CLK_SWITCHMODE_AUTO))

#define IS_CLK_CLOCKSTATE_OK(STATE) ((STATE == DISABLE) || (STATE == ENABLE))

#define IS_CLK_CLOCKPRESCALER_OK(PRESCALER) ((PRESCALER == CLK_HSI_DIV1) ||\
    (PRESCALER == CLK_HSI_DIV2) ||\
    (PRESCALER == CLK_HSI_DIV4) ||\
    (PRESCALER == CLK_HSI_DIV8))

#define IS_CLK_CSSCONFIG_OK(CSSVALUE) ((CSSVALUE == CLK_CSSR_CSSON_DIE) ||\
                                       (CSSVALUE == CLK_CSSR_CSSON) ||\
                                       (CSSVALUE == CLK_CSSR_CSSOFF))

#define IS_CLK_NEWCLOCK_OK(CLKVALUE) ((CLKVALUE == CLK_HSI) ||\
                                      (CLKVALUE == CLK_LSI) ||\
                                      (CLKVALUE == CLK_HSE))

/**
  * @}
  */

/* Exported functions ------------------------------------------------------- */

ErrorStatus CLK_Init(CLK_NewClock_TypeDef NewClock,
                     CLK_CurrentClockState_TypeDef CLK_CurrentClock,
                     FunctionalState CLK_FastHaltWakeup,
                     CLK_ClockFrequencyDivisor_TypeDef HSIPrescaler,
                     FunctionalState CLK_SwitchIT,
                     CLK_SwitchMode_TypeDef Mode,
                     CLK_StartupTime_TypeDef StartupTime,
                     FunctionalState CLK_NewState);
void CLK_DeInit(void);
void CLK_ClockSwitchConfig(FunctionalState CLK_NewState);
void CLK_HSIConfig(FunctionalState CLK_FastHaltWakeup, CLK_ClockFrequencyDivisor_TypeDef HSIPrescaler);
void CLK_LSIConfig(FunctionalState CLK_SlowActiveHalt);
void CLK_AdjustHSICalibrationValue(CLK_HSICalibrationValue_TypeDef CLK_HSICalibrationValue);
void CLK_HSECmd(FunctionalState CLK_NewState);
void CLK_HSICmd(FunctionalState CLK_NewState);
void CLK_LSICmd(FunctionalState CLK_NewState);
void CLK_PLLConfig(CLK_SpreadControl_TypeDef CLK_SpreadControl,
                   CLK_SSCGClockMode_TypeDef CLK_SSCGMode,
                   CLK_ClockBypass_TypeDef CLK_Bypass,
                   CLK_Reference_TypeDef CLK_Reference);
void CLK_PLLCmd(FunctionalState CLK_NewState);
void CLK_SYSCLKConfig(CLK_ClockFrequencyDivisor_TypeDef Divider);
CLK_ClockSources CLK_GetSYSCLKSource(void);
void CLK_SYSCLKEmergencyClear(void);
void CLK_ITConfig(CLK_ClockInterruptSource_TypeDef CLK_IT, FunctionalState CLK_NewState);
void CLK_GetClocksFreq(CLK_Clocks_TypeDef* CLK_Clocks);
void CLK_PCKEN1PeriphClockCmd(CLK_Peripherals1ClockEnable_TypeDef CLK_PCKEN_1_Periph, FunctionalState CLK_NewState);
void CLK_PCKEN2PeriphClockCmd(CLK_Peripherals2ClockEnable_TypeDef CLK_PCKEN_2_Periph, FunctionalState CLK_NewState);
FlagStatus CLK_GetFlagStatus(CLK_ClockFlagNumber_TypeDef CLK_FLAG_NUM, CLK_ClockFlagPosition_TypeDef CLK_FLAG_POS);
void CLK_ClockSecuritySystemCmd(FunctionalState CLK_NewState);
ErrorStatus CLK_CCOConfig(CLK_ClockSourceOutput_TypeDef CLK_CCO);
void CLK_CCOCmd(FunctionalState CLK_NewState);
void CLK_ClearITPendingBit(CLK_InterruptPendingClear CLK_IT);
ITStatus CLK_GetITStatus(CLK_ClockInterruptSource_TypeDef CLK_IT);
ErrorStatus CLK_SwitchClock(CLK_NewClock_TypeDef NewClock, CLK_CurrentClockState_TypeDef CLK_CurrentClock, FunctionalState CLK_SwitchIT, CLK_SwitchMode_TypeDef Mode);

#ifdef HW_PLATFORM_TEST_CHIP
void CLK_HSEConfig_TC(CLK_StabilizationTime_TypeDef CLK_StabTime, CLK_HSEOscilletorUsed_TypeDef CLK_HSEOsc);
#endif

#endif /* __ST79_CLK_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/