📄 st79_map.h
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#define USART_CR3_RESET_VALUE ((u8)0x00)
#define USART_CR4_RESET_VALUE ((u8)0x00)
#define USART_CR5_RESET_VALUE ((u8)0x00)
#define USART_GT_RESET_VALUE ((u8)0x00)
#define USART_PSCR_RESET_VALUE ((u8)0x00)
/**
* @}
*/
/** @addtogroup USART_Registers_Bits_Definition
* @{
*/
#define USART_SR_TXE ((u8)0x80) /*!< Transmit Data Register Empty Mask */
#define USART_SR_TC ((u8)0x40) /*!< Transmission Complete Mask */
#define USART_SR_RXNE ((u8)0x20) /*!< Read Data Register Not Empty Mask */
#define USART_SR_IDLE ((u8)0x10) /*!< IDLE line detected Mask */
#define USART_SR_OR ((u8)0x08) /*!< OverRun error Mask */
#define USART_SR_NF ((u8)0x04) /*!< Noise Flag Mask */
#define USART_SR_FE ((u8)0x02) /*!< Framing Error Mask */
#define USART_SR_PE ((u8)0x01) /*!< Parity Error Mask */
#define USART_BRR1_DIVM ((u8)0xFF) /*!< LSB mantissa of USARTDIV [7:0] Mask */
#define USART_BRR2_DIVM ((u8)0xF0) /*!< MSB mantissa of USARTDIV [11:8] Mask */
#define USART_BRR2_DIVF ((u8)0x0F) /*!< Fraction bits of USARTDIV [3:0] Mask */
#define USART_CR1_R8 ((u8)0x80) /*!< Receive Data bit 8 */
#define USART_CR1_T8 ((u8)0x40) /*!< Transmit data bit 8 */
#define USART_CR1_USARTD ((u8)0x20) /*!< USART Disable (for low power consumption) */
#define USART_CR1_M ((u8)0x10) /*!< Word length Mask */
#define USART_CR1_WAKE ((u8)0x08) /*!< Wake-up method Mask */
#define USART_CR1_PCEN ((u8)0x04) /*!< Parity Control Enable Mask */
#define USART_CR1_PS ((u8)0x02) /*!< USART LINBreakLength Mask */
#define USART_CR1_PIEN ((u8)0x01) /*!< USART Parity Interrupt Enable Mask */
#define USART_CR2_TIEN ((u8)0x80) /*!< Transmitter Interrupt Enable Mask */
#define USART_CR2_TCIEN ((u8)0x40) /*!< TransmissionComplete Interrupt Enable Mask*/
#define USART_CR2_RIEN ((u8)0x20) /*!< Receiver Interrupt Enable Mask */
#define USART_CR2_ILIEN ((u8)0x10) /*!< IDLE Line Interrupt Enable Mask */
#define USART_CR2_TEN ((u8)0x08) /*!< Transmitter Enable Mask */
#define USART_CR2_REN ((u8)0x04) /*!< Receiver Enable Mask */
#define USART_CR2_RWU ((u8)0x02) /*!< Receiver Wake-Up Mask */
#define USART_CR2_SBK ((u8)0x01) /*!< Send Break Mask */
#define USART_CR3_Reserved ((u8)0x80) /*!< RESERVED bit Mask */
#define USART_CR3_LINEN ((u8)0x40) /*!< Alternate Function outpu Mask */
#define USART_CR3_STOP ((u8)0x30) /*!< STOP bits [1:0] Mask */
#define USART_CR3_CLKEN ((u8)0x08) /*!< Clock Enable Mask */
#define USART_CR3_CPOL ((u8)0x04) /*!< Clock Polarity Mask */
#define USART_CR3_CPHA ((u8)0x02) /*!< Clock Phase Mask */
#define USART_CR3_LBCL ((u8)0x01) /*!< Last Bit Clock pulse Mask */
#define USART_CR4_Reserved ((u8)0x80) /*!< RESERVED bit Mask */
#define USART_CR4_LBDIEN ((u8)0x40) /*!< LIN Break Detection Interrupt Enable Mask */
#define USART_CR4_LBDL ((u8)0x20) /*!< LIN Break Detection Length Mask */
#define USART_CR4_LBDF ((u8)0x10) /*!< LIN Break Detection Flag Mask */
#define USART_CR4_ADD ((u8)0x0F) /*!< Address of the USART node Mask */
#define USART_CR5_Reserved ((u8)0xC1) /*!< RESERVED bit Mask */
#define USART_CR5_SCEN ((u8)0x20) /*!Smart Card Enable Mask */
#define USART_CR5_NACK ((u8)0x10) /*!Smart Card Nack Enable Mask */
#define USART_CR5_HDSEL ((u8)0x08) /*!< Half-Duplex Selection Mask */
#define USART_CR5_IRLP ((u8)0x04) /*!< Irda Low Power Selection Mask */
#define USART_CR5_IREN ((u8)0x02) /*!< Irda Enable Mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief LINUART
*/
typedef volatile struct LINUART_struct
{
u8 SR; /* LINUART status register */
u8 DR; /* LINUART data register */
u8 BRR1; /* LINUART baud rate register */
u8 BRR2; /* LINUART DIV mantissa[11:8] SCIDIV fraction */
u8 CR1; /* LINUART control register 1 */
u8 CR2; /* LINUART control register 2 */
u8 CR3; /* LINUART control register 3 */
u8 CR4; /* LINUART control register 4 */
u8 dummy;
u8 CR5; /* LINUART control register 5 */
}
LINUART_TypeDef;
/** @addtogroup LINUART_Registers_Reset_Value
* @{
*/
#define LINUART_SR_RESET_VALUE ((u8)0xC0)
#define LINUART_BRR1_RESET_VALUE ((u8)0x00)
#define LINUART_BRR2_RESET_VALUE ((u8)0x00)
#define LINUART_CR1_RESET_VALUE ((u8)0x00)
#define LINUART_CR2_RESET_VALUE ((u8)0x00)
#define LINUART_CR3_RESET_VALUE ((u8)0x00)
#define LINUART_CR4_RESET_VALUE ((u8)0x00)
#define LINUART_CR5_RESET_VALUE ((u8)0x00)
/**
* @}
*/
/** @addtogroup LINUART_Registers_Bits_Definition
* @{
*/
#define LINUART_SR_TXE ((u8)0x80) /*!< Transmit Data Register Empty Mask */
#define LINUART_SR_TC ((u8)0x40) /*!< Transmission Complete Mask */
#define LINUART_SR_RXNE ((u8)0x20) /*!< Read Data Register Not Empty Mask */
#define LINUART_SR_IDLE ((u8)0x10) /*!< IDLE line detected Mask */
#define LINUART_SR_OR ((u8)0x08) /*!< OverRun error Mask */
#define LINUART_SR_NF ((u8)0x04) /*!< Noise Flag Mask */
#define LINUART_SR_FE ((u8)0x02) /*!< Framing Error Mask */
#define LINUART_SR_PE ((u8)0x01) /*!< Parity Error Mask */
#define LINUART_BRR1_DIVM ((u8)0xFF) /*!< LSB mantissa of LINUARTDIV [7:0] Mask */
#define LINUART_BRR2_DIVM ((u8)0xF0) /*!< MSB mantissa of LINUARTDIV [11:8] Mask */
#define LINUART_BRR2_DIVF ((u8)0x0F) /*!< Fraction bits of LINUARTDIV [3:0] Mask */
#define LINUART_CR1_R8 ((u8)0x80) /*!< Receive Data bit 8 */
#define LINUART_CR1_T8 ((u8)0x40) /*!< Transmit data bit 8 */
#define LINUART_CR1_USARTD ((u8)0x20) /*!< LINUART Disable (for low power consumption) */
#define LINUART_CR1_M ((u8)0x10) /*!< Word length Mask */
#define LINUART_CR1_WAKE ((u8)0x08) /*!< Wake-up method Mask */
#define LINUART_CR1_PCEN ((u8)0x04) /*!< Parity Control Enable Mask */
#define LINUART_CR1_PS ((u8)0x02) /*!< LINUART LINBreakLength Mask */
#define LINUART_CR1_PIEN ((u8)0x01) /*!< LINUART Parity Enable Mask */
#define LINUART_CR2_TIEN ((u8)0x80) /*!< Transmitter Interrupt Enable Mask */
#define LINUART_CR2_TCIEN ((u8)0x40) /*!< TransmissionComplete Interrupt Enable Mask*/
#define LINUART_CR2_RIEN ((u8)0x20) /*!< Receiver Interrupt Enable Mask */
#define LINUART_CR2_ILIEN ((u8)0x10) /*!< IDLE Line Interrupt Enable Mask */
#define LINUART_CR2_TEN ((u8)0x08) /*!< Transmitter Enable Mask */
#define LINUART_CR2_REN ((u8)0x04) /*!< Receiver Enable Mask */
#define LINUART_CR2_RWU ((u8)0x02) /*!< Receiver Wake-Up Mask */
#define LINUART_CR2_SBK ((u8)0x01) /*!< Send Break Mask */
#define LINUART_CR3_Reserved ((u8)0x8F) /*!< RESERVED bit Mask */
#define LINUART_CR3_LINEN ((u8)0x40) /*!< Alternate Function outpu Mask */
#define LINUART_CR3_STOP ((u8)0x30) /*!< STOP bits [1:0] Mask */
#define LINUART_CR4_Reserved ((u8)0x80) /*!< RESERVED bit Mask */
#define LINUART_CR4_LBDIEN ((u8)0x40) /*!< LIN Break Detection Interrupt Enable Mask */
#define LINUART_CR4_LBDL ((u8)0x20) /*!< LIN Break Detection Length Mask */
#define LINUART_CR4_LBDF ((u8)0x10) /*!< LIN Break Detection Flag Mask */
#define LINUART_CR4_ADD ((u8)0x0F) /*!< Address of the LINUART node Mask */
#define LINUART_CR5_Reserved ((u8)0x48) /*!< RESERVED bit Mask */
#define LINUART_CR5_LDUM ((u8)0x80) /*! <LIN Divider Update Method*/
#define LINUART_CR5_LSLV ((u8)0x20) /*!< LIN Slave Enable */
#define LINUART_CR5_LASE ((u8)0x10) /*!<LIN Autosynchronization Enable */
#define LINUART_CR5_LHDIEN ((u8)0x04) /*!< LIN Header Detection Interrupt Enable */
#define LINUART_CR5_LHDF ((u8)0x02) /*!< LIN Header Detection Flag */
#define LINUART_CR5_LSF ((u8)0x01) /*!< LIN Synch Field */
/**
* @}
*/
/** @addtogroup CPU_Registers_Bits_Definition
* @{
*/
#define CPU_CC_I1I0 ((u8)0x28) /*!< Condition Code register, I1 and I0 bits mask */
/**
* @}
*/
/******************************************************************************/
/* Peripherals Base Address */
/******************************************************************************/
#ifdef HW_PLATFORM_TEST_CHIP
#define GPIOA_BaseAddress 0x5000
#define GPIOB_BaseAddress 0x5005
#define GPIOC_BaseAddress 0x500A
#define GPIOD_BaseAddress 0x500F
#define GPIOE_BaseAddress 0x5014
#define GPIOF_BaseAddress 0x5019
#define GPIOG_BaseAddress 0x501E
#define GPIOH_BaseAddress 0x5023
#define GPIOI_BaseAddress 0x5028
#define FLASH_BaseAddress 0x505A
#define OPT_BaseAddress 0x5067
#define EXTI_BaseAddress 0x50A0
#define RST_BaseAddress 0x50B0
#define CLK_BaseAddress 0x50C0
#define WWDG_BaseAddress 0x50D1
#define IWDG_BaseAddress 0x50E0
#define AWUBEEP_BaseAddress 0x50F0
#define SPI_BaseAddress 0x5200
#define I2C_BaseAddress 0x5210
#define USART_BaseAddress 0x5230
#define LINUART_BaseAddress 0x5240
#define TIM1_BaseAddress 0x5250
#define TIM2_BaseAddress 0x5300
#define TIM3_BaseAddress 0x5320
#define TIM4_BaseAddress 0x5340
#define ADC_BaseAddress 0x5400
#define ITC_BaseAddress 0x7F70
#define SWIM_BaseAddress 0x7F80
#define DM_BaseAddress 0x7F90
#endif /* HW_PLATFORM_TEST_CHIP */
#ifdef HW_PLATFORM_CUT10
#define GPIOA_BaseAddress 0x5000
#define GPIOB_BaseAddress 0x5005
#define GPIOC_BaseAddress 0x500A
#define GPIOD_BaseAddress 0x500F
#define GPIOE_BaseAddress 0x5014
#define GPIOF_BaseAddress 0x5019
#define GPIOG_BaseAddress 0x501E
#define GPIOH_BaseAddress 0x5023
#define GPIOI_BaseAddress 0x5028
#define FLASH_BaseAddress 0x505A
#define OPT_BaseAddress 0x5067
#define EXTI_BaseAddress 0x50A0
#define RST_BaseAddress 0x50B0
#define CLK_BaseAddress 0x50C0
#define WWDG_BaseAddress 0x50D1
#define IWDG_BaseAddress 0x50E0
#define AWUBEEP_BaseAddress 0x50F0
#define SPI_BaseAddress 0x5200
#define I2C_BaseAddress 0x5210
#define USART_BaseAddress 0x5230
#define LINUART_BaseAddress 0x5240
#define TIM1_BaseAddress 0x5250
#define TIM2_BaseAddress 0x5300
#define TIM3_BaseAddress 0x5320
#define TIM4_BaseAddress 0x5340
#define ADC_BaseAddress 0x5400
#define ITC_BaseAddress 0x7F70
#define SWIM_BaseAddress 0x7F80
#define DM_BaseAddress 0x7F90
#endif /* HW_PLATFORM_CUT10 */
/******************************************************************************/
/* Peripherals declarations */
/******************************************************************************/
#ifdef _GPIOA
#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
#endif
#ifdef _GPIOB
#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
#endif
#ifdef _GPIOC
#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
#endif
#ifdef _GPIOD
#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
#endif
#ifdef _GPIOE
#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
#endif
#ifdef _GPIOF
#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
#endif
#ifdef _GPIOG
#define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
#endif
#ifdef _GPIOH
#define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
#endif
#ifdef _GPIOI
#define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
#endif
#ifdef _FLASH
#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
#endif
#ifdef _OPT
#define OPT ((OPT_TypeDef *) OPT_BaseAddress)
#endif
#ifdef _EXTI
#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
#endif
#ifdef _RST
#define RST ((RST_TypeDef *) RST_BaseAddress)
#endif
#ifdef _CLK
#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
#endif
#ifdef _WWDG
#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
#endif
#ifdef _IWDG
#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
#endif
#ifdef _AWUBEEP
#define AWU ((AWUBEEP_TypeDef *) AWUBEEP_BaseAddress)
#endif
#ifdef _SPI
#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
#endif
#ifdef _I2C
#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
#endif
#ifdef _USART
#define USART ((USART_TypeDef *) USART_BaseAddress)
#endif
#ifdef _LINUART
#define LINUART ((LINUART_TypeDef *) LINUART_BaseAddress)
#endif
#ifdef _TIM1
#define TIM1 ((HTIM_TypeDef *) TIM1_BaseAddress)
#endif
#ifdef _TIM2
#define TIM2 ((MTIM_TypeDef *) TIM2_BaseAddress)
#endif
#ifdef _TIM3
#define TIM3 ((MTIM_TypeDef *) TIM3_BaseAddress)
#endif
#ifdef _TIM4
#define TIM4 ((STIM_TypeDef *) TIM4_BaseAddress)
#endif
#ifdef _ADC
#define ADC ((ADC_TypeDef *) ADC_BaseAddress)
#endif
#ifdef _ITC
#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
#endif
#ifdef _SWIM
#define SWIM ((SWIM_TypeDef *) SWIM_BaseAddress)
#endif
#ifdef _DM
#define DM ((DM_TypeDef *) DM_BaseAddress)
#endif
#endif /* __ST79_MAP_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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