st79_map.h

st公司新出的一款8位单片机st79的lib库

#define HTIM_IER_Reserved  ((u8)0x10) /*!< Reserved Bit Mask. */
#define HTIM_IER_CC3IE     ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable Mask. */
#define HTIM_IER_CC2IE     ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable Mask. */
#define HTIM_IER_CC1IE     ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable Mask. */
#define HTIM_IER_UIE       ((u8)0x01) /*!< Update Interrupt Enable Mask. */

#define HTIM_SR1_BIF       ((u8)0x80) /*!< Break Interrupt Flag Mask. */
#define HTIM_SR1_TIF       ((u8)0x40) /*!< Trigger Interrupt Flag Mask. */
#define HTIM_SR1_CCUIF     ((u8)0x20) /*!< CC-Update Interrupt Flag Mask. */
#define HTIM_SR1_Reserved  ((u8)0x10) /*!< Reserved Bit Mask. */
#define HTIM_SR1_CC3IF     ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag Mask. */
#define HTIM_SR1_CC2IF     ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag Mask. */
#define HTIM_SR1_CC1IF     ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag Mask. */
#define HTIM_SR1_UIF       ((u8)0x01) /*!< Update Interrupt Flag Mask. */

#define HTIM_SR2_Reserved  ((u8)0xF1) /*!< Reserved Bit Mask. */
#define HTIM_SR2_CC3OF     ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag Mask. */
#define HTIM_SR2_CC2OF     ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag Mask. */
#define HTIM_SR2_CC1OF     ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag Mask. */

#define HTIM_EGR_BG         ((u8)0x80) /*!< Break Generation Mask. */
#define HTIM_EGR_TG         ((u8)0x40) /*!< Trigger Generation Mask. */
#define HTIM_EGR_CCUG       ((u8)0x20) /*!< Capture/Compare Control Update Generation Mask. */
#define HTIM_EGR_Reserved   ((u8)0x10) /*!< Reserved Bit Mask. */
#define HTIM_EGR_CC3G       ((u8)0x08) /*!< Capture/Compare 3 Generation Mask. */
#define HTIM_EGR_CC2G       ((u8)0x04) /*!< Capture/Compare 2 Generation Mask. */
#define HTIM_EGR_CC1G       ((u8)0x02) /*!< Capture/Compare 1 Generation Mask. */
#define HTIM_EGR_UG         ((u8)0x01) /*!< Update Generation Mask. */

#define HTIM_CCMR1_OC1CE    ((u8)0x80) /*!< Output Compare 1 Clear Enable Mask. */
#define HTIM_CCMR1_OC1M     ((u8)0x70) /*!< Output Compare 1 Mode Mask. */
#define HTIM_CCMR1_OC1PE    ((u8)0x08) /*!< Output Compare 1 Preload Enable Mask. */
#define HTIM_CCMR1_OC1FE    ((u8)0x04) /*!< Output Compare 1 Fast Enable Mask. */
#define HTIM_CCMR1_CC1S     ((u8)0x03) /*!< Capture/Compare 1 Selection Mask. */
#define HTIM_CCMR1_IC1F     ((u8)0xF0) /*!< Input Capture 1 Filter Mask. */
#define HTIM_CCMR1_IC1PSC   ((u8)0x0C) /*!< Input Capture 1 Prescaler Mask. */

#define HTIM_CCMR2_OC2CE    ((u8)0x80) /*!< Output Compare 2 Clear Enable Mask. */
#define HTIM_CCMR2_OC2M     ((u8)0x70) /*!< Output Compare 2 Mode Mask. */
#define HTIM_CCMR2_OC2PE    ((u8)0x08) /*!< Output Compare 2 Preload Enable Mask. */
#define HTIM_CCMR2_OC2FE    ((u8)0x04) /*!< Output Compare 2 Fast Enable Mask. */
#define HTIM_CCMR2_CC2S     ((u8)0x03) /*!< Capture/Compare 2 Selection Mask. */
#define HTIM_CCMR2_IC2F     ((u8)0xF0) /*!< Input Capture 2 Filter Mask. */
#define HTIM_CCMR2_IC2PSC   ((u8)0x0C) /*!< Input Capture 2 Prescaler Mask. */

#define HTIM_CCMR3_OC3CE    ((u8)0x80) /*!< Output Compare 3 Clear Enable Mask. */
#define HTIM_CCMR3_OC3M     ((u8)0x70) /*!< Output Compare 3 Mode Mask. */
#define HTIM_CCMR3_OC3PE    ((u8)0x08) /*!< Output Compare 3 Preload Enable Mask. */
#define HTIM_CCMR3_OC3FE    ((u8)0x04) /*!< Output Compare 3 Fast Enable Mask. */
#define HTIM_CCMR3_CC3S     ((u8)0x03) /*!< Capture/Compare 3 Selection Mask. */
#define HTIM_CCMR3_IC3F     ((u8)0xF0) /*!< Input Capture 3 Filter Mask. */
#define HTIM_CCMR3_IC3PSC   ((u8)0x0C) /*!< Input Capture 3 Prescaler Mask. */

#ifdef HW_PLATFORM_CUT10
#define HTIM_CCMR4_OC4CE    ((u8)0x80) /*!< Output Compare 4 Clear Enable Mask. */
#define HTIM_CCMR4_OC4M     ((u8)0x70) /*!< Output Compare 4 Mode Mask. */
#define HTIM_CCMR4_OC4PE    ((u8)0x08) /*!< Output Compare 4 Preload Enable Mask. */
#define HTIM_CCMR4_OC4FE    ((u8)0x04) /*!< Output Compare 4 Fast Enable Mask. */
#define HTIM_CCMR4_CC4S     ((u8)0x03) /*!< Capture/Compare 4 Selection Mask. */
#define HTIM_CCMR4_IC4F     ((u8)0xF0) /*!< Input Capture 4 Filter Mask. */
#define HTIM_CCMR4_IC4PSC   ((u8)0x0C) /*!< Input Capture 4 Prescaler Mask. */
#endif

#define HTIM_CCER1_CC2NP    ((u8)0x80) /*!< Capture/Compare 2 Complementary output Polarity Mask. */
#define HTIM_CCER1_CC2NE    ((u8)0x40) /*!< Capture/Compare 2 Complementary output enable Mask. */
#define HTIM_CCER1_CC2P     ((u8)0x20) /*!< Capture/Compare 2 output Polarity Mask. */
#define HTIM_CCER1_CC2E     ((u8)0x10) /*!< Capture/Compare 2 output enable Mask. */
#define HTIM_CCER1_CC1NP    ((u8)0x08) /*!< Capture/Compare 1 Complementary output Polarity Mask. */
#define HTIM_CCER1_CC1NE    ((u8)0x04) /*!< Capture/Compare 1 Complementary output enable Mask. */
#define HTIM_CCER1_CC1P     ((u8)0x02) /*!< Capture/Compare 1 output Polarity Mask. */
#define HTIM_CCER1_CC1E     ((u8)0x01) /*!< Capture/Compare 1 output enable Mask. */

#define HTIM_CCER2_CC4NP    ((u8)0x80) /*!< Capture/Compare 4 Complementary output Polarity Mask. */
#define HTIM_CCER2_CC4NE    ((u8)0x40) /*!< Capture/Compare 4 Complementary output enable Mask. */
#define HTIM_CCER2_CC4P     ((u8)0x20) /*!< Capture/Compare 4 output Polarity Mask. */
#define HTIM_CCER2_CC4E     ((u8)0x10) /*!< Capture/Compare 4 output enable Mask. */
#define HTIM_CCER2_CC3NP    ((u8)0x08) /*!< Capture/Compare 3 Complementary output Polarity Mask. */
#define HTIM_CCER2_CC3NE    ((u8)0x04) /*!< Capture/Compare 3 Complementary output enable Mask. */
#define HTIM_CCER2_CC3P     ((u8)0x02) /*!< Capture/Compare 3 output Polarity Mask. */
#define HTIM_CCER2_CC3E     ((u8)0x01) /*!< Capture/Compare 3 output enable Mask. */

#define HTIM_CNTRH_CNT      ((u8)0xFF) /*!<Counter Value (MSB) Mask. */
#define HTIM_CNTRL_CNT      ((u8)0xFF) /*!<Counter Value (LSB) Mask. */

#define HTIM_PSCH_PSC      ((u8)0xFF) /*!<Prescaler Value (MSB) Mask. */
#define HTIM_PSCL_PSC      ((u8)0xFF) /*!<Prescaler Value (LSB) Mask. */

#define HTIM_ARRH_ARR      ((u8)0xFF) /*!<Autoreload Value (MSB) Mask. */
#define HTIM_ARRL_ARR 	   ((u8)0xFF) /*!<Autoreload Value (LSB) Mask. */

#define HTIM_RCR_REP       ((u8)0xFF) /*!<Repetition Counter Value Mask. */

#define HTIM_CCR1H_CCR1    ((u8)0xFF) /*!<Capture/Compare 1 Value (MSB) Mask. */
#define HTIM_CCR1L_CCR1    ((u8)0xFF) /*!<Capture/Compare 1 Value (LSB) Mask. */

#define HTIM_CCR2H_CCR2    ((u8)0xFF) /*!<Capture/Compare 2 Value (MSB) Mask. */
#define HTIM_CCR2L_CCR2    ((u8)0xFF) /*!<Capture/Compare 2 Value (LSB) Mask. */

#define HTIM_CCR3H_CCR3    ((u8)0xFF) /*!<Capture/Compare 3 Value (MSB) Mask. */
#define HTIM_CCR3L_CCR3    ((u8)0xFF) /*!<Capture/Compare 3 Value (LSB) Mask. */

#ifdef HW_PLATFORM_CUT10
#define HTIM_CCR4H_CCR4    ((u8)0xFF) /*!<Capture/Compare 4 Value (MSB) Mask. */
#define HTIM_CCR4L_CCR4    ((u8)0xFF) /*!<Capture/Compare 4 Value (LSB) Mask. */
#endif

#define HTIM_BKR_MOE       ((u8)0x80) /*!<Main Output Enable Mask. */
#define HTIM_BKR_AOE       ((u8)0x40) /*!<Automatic Output Enable Mask. */
#define HTIM_BKR_BKP       ((u8)0x20) /*!<Break Polarity Mask. */
#define HTIM_BKR_BKE       ((u8)0x10) /*!<Break Enable Mask. */
#define HTIM_BKR_Reserved  ((u8)0x08) /*!<Reserved Bit Mask. */
#define HTIM_BKR_OSSI      ((u8)0x04) /*!<Off-State Selection for Idle mode Mask. */
#define HTIM_BKR_LOCK      ((u8)0x03) /*!<Lock Configuration Mask. */

#define HTIM_DTR_DTR       ((u8)0xFF) /*!<LDead-Time Generator set-up Mask. */

#define HTIM_OISR_Reserved ((u8)0xC0) /*!<Reserved Bit Mask. */
#define HTIM_OISR_OIS3N    ((u8)0x20) /*!<Output Idle state 3 (OC3N output) Mask. */
#define HTIM_OISR_OIS3     ((u8)0x10) /*!<Output Idle state 3 (OC3 output) Mask. */
#define HTIM_OISR_OIS2N    ((u8)0x08) /*!<Output Idle state 2 (OC2N output) Mask. */
#define HTIM_OISR_OIS2     ((u8)0x04) /*!<Output Idle state 2 (OC2 output) Mask. */
#define HTIM_OISR_OIS1N    ((u8)0x02) /*!<Output Idle state 1 (OC1N output) Mask. */
#define HTIM_OISR_OIS1     ((u8)0x01) /*!<Output Idle state 1 (OC1 output) Mask. */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Medium End Timer (MTIM)
  */
typedef volatile struct MTIM_struct
{
  u8 CR1;  /*control register 1   */
  u8 IER;  /*interrupt enable register*/
  u8 SR1;  /*status register 1   */
  u8 SR2;  /*status register 2    */
  u8 EGR;  /*event generation register */
  u8 CCMR1;  /*CC mode register 1     */
  u8 CCMR2;  /*CC mode register 2     */
  u8 CCMR3;  /*CC mode register 3      */
  u8 CCER1;  /*CC enable register 1     */
  u8 CCER2;  /*CC enable register 2    */
  u8 CNTRH;  /*counter high     */
  u8 CNTRL;  /*counter low       */
  u8 PSCL;  /*prescaler low    */
  u8 ARRH;  /*auto-reload register high  */
  u8 ARRL;  /*auto-reload register low    */
  u8 CCR1H;  /*capture/compare register 1 high */
  u8 CCR1L;  /*capture/compare register 1 low   */
  u8 CCR2H;  /*capture/compare register 2 high   */
  u8 CCR2L;  /*capture/compare register 2 low     */
  u8 CCR3H;  /*capture/compare register 3 high    */
  u8 CCR3L;  /*capture/compare register 3 low      */
  u8 BKR_DUM;/*dummy register for gpt1_itrx_ml_s patterns */
}
MTIM_TypeDef;

/*----------------------------------------------------------------------------*/
/**
  * @brief System or Low End Timer (STIM)
  */
typedef volatile struct STIM_struct
{
  u8 CR1; /*control register 1 */
  u8 IER; /*interrupt enable register  */
  u8 SR1; /*status register 1    */
  u8 EGR; /*event generation register */
  u8 CNTL; /*counter low  */
  u8 PSCL; /*prescaler low   */
  u8 ARRL; /*auto-reload register low */
#ifdef HW_PLATFORM_TEST_CHIP
  u8 BKR_DUM; /*dummy register for gpt1_itrx_ml_s patterns */
#endif
}
STIM_TypeDef;
/** @addtogroup STIM_Registers_Reset_Value
  * @{
  */
#define STIM_CR1_RESET_VALUE    ((u8)0x00)
#define STIM_IER_RESET_VALUE    ((u8)0x00)
#define STIM_SR1_RESET_VALUE    ((u8)0x00)
#define STIM_EGR_RESET_VALUE    ((u8)0x00)
#define STIM_CNTL_RESET_VALUE    ((u8)0x00)
#define STIM_PSCL_RESET_VALUE    ((u8)0x00)
#define STIM_ARRL_RESET_VALUE    ((u8)0xFF)

  /**
  * @}
  */

/** @addtogroup STIM_Registers_Bits_Definition
  * @{
  */
#define STIM_CR1_ARPE     ((u8)0x80) /*!< Auto-Reload Preload Enable Mask. */
#define STIM_CR1_Reserved ((u8)0x07) /*!< Reserved Bit Mask. */
#define STIM_CR1_OPM      ((u8)0x08) /*!< One Pulse Mode Mask. */
#define STIM_CR1_URS      ((u8)0x04) /*!< Update Request Source Mask. */
#define STIM_CR1_UDIS     ((u8)0x02) /*!< Update DIsable Mask. */
#define STIM_CR1_CEN      ((u8)0x01) /*!< Counter Enable Mask. */

#define STIM_IER_Reserved  ((u8)0xFE) /*!< Reserved Bit Mask. */
#define STIM_IER_UIE       ((u8)0x01) /*!< Update Interrupt Enable Mask. */

#define STIM_SR1_Reserved  ((u8)0xFE) /*!< Reserved Bit Mask. */
#define STIM_SR1_UIF       ((u8)0x01) /*!< Update Interrupt Flag Mask. */

#define STIM_EGR_Reserved   ((u8)0xFE) /*!< Reserved Bit Mask. */
#define STIM_EGR_UG         ((u8)0x01) /*!< Update Generation Mask. */

#define STIM_CNTRL_CNT      ((u8)0xFF) /*!<Counter Value (LSB) Mask. */

#define STIM_PSCL_Reserved ((u8)0xF8) /*!< Reserved Bit Mask. */
#define STIM_PSCL_PSC      ((u8)0x07) /*!<Prescaler Value (LSB) Mask. */

#define STIM_ARRL_ARR 	   ((u8)0xFF) /*!<Autoreload Value (LSB) Mask. */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Inter-Integrated Circuit (I2C)
  */
typedef volatile struct I2C_struct
{
  u8 CR1;    /*!< I2C control register 1 */
  u8 CR2;    /*!< I2C control register 2 */
  u8 FREQR;  /*!< I2C frequency register */
  u8 OARL;   /*!< I2C own address register LSB */
  u8 OARH;   /*!< I2C own address register MSB */
#ifdef HW_PLATFORM_TEST_CHIP
  u8 OAR2;   /*!< I2C own address register dual */ /* TBD not in datasheet */
#else
  u8 RESERVED1;
#endif
  u8 DR;     /*!< I2C data register */
  u8 SR1;    /*!< I2C status register 1 */
  u8 SR2;    /*!< I2C status register 2 */
  u8 SR3;    /*!< I2C status register 3 */
  u8 ITR;    /*!< I2C interrupt register */
  u8 CCRL;   /*!< I2C clock control register low */
  u8 CCRH;   /*!< I2C clock control register high */
  u8 TRISER; /*!< I2C maximum rise time register */
#ifdef HW_PLATFORM_TEST_CHIP  
  u8 PECR;   /*!< I2C packet error checking register */ /* TBD not in datasheet */
#else
  u8 RESERVED2;
#endif
}
I2C_TypeDef;

/** @addtogroup I2C_Registers_Reset_Value
  * @{
  */
#define I2C_CR1_RESET_VALUE    ((u8)0x00)
#define I2C_CR2_RESET_VALUE    ((u8)0x00)
#define I2C_FREQR_RESET_VALUE  ((u8)0x00)
#define I2C_OARL_RESET_VALUE   ((u8)0x00)
#define I2C_OARH_RESET_VALUE   ((u8)0x00)
#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_OAR2_RESET_VALUE   ((u8)0x00) /* TBD not in datasheet */
#endif
#define I2C_DR_RESET_VALUE     ((u8)0x00)
#define I2C_SR1_RESET_VALUE    ((u8)0x00)
#define I2C_SR2_RESET_VALUE    ((u8)0x00)
#define I2C_SR3_RESET_VALUE    ((u8)0x00)
#define I2C_ITR_RESET_VALUE    ((u8)0x00)
#define I2C_CCRL_RESET_VALUE   ((u8)0x00)
#define I2C_CCRH_RESET_VALUE   ((u8)0x00)
#define I2C_TRISER_RESET_VALUE ((u8)0x00)
#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_PECR_RESET_VALUE   ((u8)0x00)
#endif
/**
  * @}
  */

/** @addtogroup I2C_Registers_Bits_Definition
  * @{
  */

#define I2C_CR1_NOSTRETCH ((u8)0x80) /*!< Clock Stretching Disable (Slave mode) */
#define I2C_CR1_ENGC      ((u8)0x40) /*!< General Call Enable */
#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_CR1_ENPEC     ((u8)0x20) /*!< */ /* TBD not in datasheet */
#define I2C_CR1_ENARP     ((u8)0x10) /*!< */ /* TBD not in datasheet */
#endif
#define I2C_CR1_PE        ((u8)0x01) /*!< Peripheral Enable */

#define I2C_CR2_SWRST ((u8)0x80) /*!< Software Reset */
#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_CR2_PEC   ((u8)0x10) /*!< */
#endif
#define I2C_CR2_POS   ((u8)0x08) /*!< Acknowledge */
#define I2C_CR2_ACK   ((u8)0x04) /*!< Acknowledge Enable */
#define I2C_CR2_STOP  ((u8)0x02) /*!< Stop Generation */
#define I2C_CR2_START ((u8)0x01) /*!< Start Generation */

#define I2C_FREQR_FREQ ((u8)0x3F) /*!< Peripheral Clock Frequency */

#define I2C_OARL_ADD  ((u8)0xFE) /*!< Interface Address bits [7..1] */
#define I2C_OARL_ADD0 ((u8)0x01) /*!< Interface Address bit0 */

#define I2C_OARH_ADDMODE  ((u8)0x80) /*!< Addressing Mode (Slave mode) */
#define I2C_OARH_RESERVED ((u8)0x40) /*!< */ /* TBD : change bit name in the datasheet ? */
#define I2C_OARH_ADD      ((u8)0x06) /*!< Interface Address bits [9..8] */

#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_OAR2_ADD ((u8)0xFF) /*!< */ /* TBD not in datasheet */
#endif

#define I2C_DR_DR ((u8)0xFF) /*!< Data Register */

#define I2C_SR1_TXE   ((u8)0x80) /*!< Data Register Empty (transmitters) */
#define I2C_SR1_RXNE  ((u8)0x40) /*!< Data Register not Empty (receivers) */
#define I2C_SR1_STOPF ((u8)0x10) /*!< Stop detection (Slave mode) */
#define I2C_SR1_ADD10 ((u8)0x08) /*!< 10-bit header sent (Master mode) */
#define I2C_SR1_BTF   ((u8)0x04) /*!< Byte Transfer Finished */
#define I2C_SR1_ADDR  ((u8)0x02) /*!< Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_SB    ((u8)0x01) /*!< Start Bit (Master mode) */

#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_SR2_TIMEOUT ((u8)0x40) /*!< */ /* TBD not in datasheet */
#endif
#define I2C_SR2_WUFH    ((u8)0x20) /*!< Wake-up from Halt */
#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_SR2_PECERR  ((u8)0x10) /*!< */ /* TBD not in datasheet */
#endif
#define I2C_SR2_OVR     ((u8)0x08) /*!< Overrun/Underrun */
#define I2C_SR2_AF      ((u8)0x04) /*!< Acknowledge Failure */
#define I2C_SR2_ARLO    ((u8)0x02) /*!< Arbitration Lost (master mode) */
#define I2C_SR2_BERR    ((u8)0x01) /*!< Bus Error */

#define I2C_SR3_GENCALL ((u8)0x10) /*!< General Call Header (Slave mode) */
#define I2C_SR3_TRA     ((u8)0x04) /*!< Transmitter/Receiver */
#define I2C_SR3_BUSY    ((u8)0x02) /*!< Bus Busy */
#define I2C_SR3_MSL     ((u8)0x01) /*!< Master/Slave */

#define I2C_ITR_ITBUFEN ((u8)0x04) /*!< Buffer Interrupt Enable */
#define I2C_ITR_ITEVTEN ((u8)0x02) /*!< Event Interrupt Enable */
#define I2C_ITR_ITERREN ((u8)0x01) /*!< Error Interrupt Enable */

#define I2C_CCRL_CCR ((u8)0xFF) /*!< Clock Control Register (Master mode) */

#define I2C_CCRH_FS   ((u8)0x80) /*!< Master Mode Selection */
#define I2C_CCRH_DUTY ((u8)0x40) /*!< Fast Mode Duty Cycle */
#define I2C_CCRH_CCR  ((u8)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */