st79_map.h

st公司新出的一款8位单片机st79的lib库

/**
  ******************************************************************************
  * @file st79_map.h
  * @brief This file contains all HW registers definitions and memory mapping.
  * @author STMicroelectronics - MCD & APG Car Body Application Labs
  * @version V0.01
  * @date 04-JUL-2007  
  ******************************************************************************
  *
  * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2007 STMicroelectronics</center></h2>
  * @image html logo.bmp
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __ST79_MAP_H
#define __ST79_MAP_H

/* Includes ------------------------------------------------------------------*/
#include "st79_conf.h"

/* Exported types ------------------------------------------------------------*/

/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/

/*----------------------------------------------------------------------------*/
/**
  * @brief Analog to Digital Converter (ADC)
  */
typedef volatile struct ADC_struct
{
  u8 CSR;  /*!< ADC control status register */
  u8 CFGR1; /*!< ADC configuration 1 */
  u8 CFGR2; /*!< ADC configuration 2 */
  u8 CFGR3; /*!< ADC configuration 3 */
  u8 DRH;   /*!< ADC Data high */
  u8 DRL;   /*!< ADC Data low */
  u8 STERL;  /*!< ADC Schmitt trigger enable MSB */
  u8 STERM;  /*!< ADC Schmitt trigger enable LSB */
}
ADC_TypeDef;

#define ADC_CFG1_ADCPRE_Set_Mask   ((u8)0x70) /* ADC register bit mask */
#define ADC_RESET_VALUE						((u8)0x00) /* Default register value*/ 
#define ADC_CSR_EOC								((u8)0x80) /* End of Conversion Empty Mask*/
#define ADC_CSR_ITEN							((u8)0x20) /* Interrupt Enable for EOC Mask*/
#define ADC_CSR_CLEARCHANNEl			((u8)0xF0) /* Interrupt Enable for EOC Mask*/
#define ADC_CFGR1_ADON						((u8)0x01) /* A/D Converter on/off Mask*/
#define ADC_CFGR1_CONT						((u8)0x02) /* A/D Converter on/off Mask*/
#define ADC_CFGR2_EXTSELMASK			((u8)0x70) /* A/D Converter on/off Mask*/


/*----------------------------------------------------------------------------*/
/**
  * @brief Auto Wake Up and Beep (AWUBEEP) peripheral registers.
  */
typedef volatile struct AWUBEEP_struct
{
  u8 CSR1; /*!< AWU Control status register 1 */
  u8 APR;  /*!< AWU Asynchronous prescalar buffer */
  u8 TBR;  /*!< AWU Time base Selection register */
  u8 CSR2; /*!< AWU Control status register 2 */
}
AWUBEEP_TypeDef;

/** @addtogroup AWUBEEP_Registers_Reset_Value
  * @{
  */
#define AWU_CSR1_RESET_VALUE ((u8)0x00)
#define AWU_APR_RESET_VALUE  ((u8)0x3F)
#define AWU_TBR_RESET_VALUE  ((u8)0x00)
#define AWU_CSR2_RESET_VALUE ((u8)0x1F)
/**
  * @}
  */

/** @addtogroup AWUBEEP_Registers_Bits_Definition
  * @{
  */
#define AWU_CSR1_AWUF    ((u8)0x20) /*!< Interrupt flag Mask */
#define AWU_CSR1_AWUEN   ((u8)0x10) /*!< Auto Wake-up enable Mask */
#define AWU_CSR1_MR      ((u8)0x02) /*!< Master Reset Mask */
#define AWU_CSR1_MSR     ((u8)0x01) /*!< Measurement enable Mask */

#define AWU_APR_APR      ((u8)0x3F) /*!< Asynchronous Prescaler divider Mask */

#define AWU_TBR_AWUTB    ((u8)0x0F) /*!< Timebase selection Mask */

#define AWU_CSR2_BEEPSEL ((u8)0xC0) /*!< Beeper frequency selection Mask */
#define AWU_CSR2_BEEPEN  ((u8)0x20) /*!< Beeper enable Mask */
#define AWU_CSR2_BEEPDIV ((u8)0x1F) /*!< Beeper Divider prescalar Mask */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Clock Controller (CLK)
  */
typedef volatile struct CLK_struct
{
  u8 ICKR;        /*!< Internal Clocks Control Register */
  u8 ECKR;        /*!< External Clocks Control Register */
#ifdef HW_PLATFORM_TEST_CHIP
  u8 PLLR;     /*!< PLL CONTROL REGISTER*/
#else
  u8 NotUsed;     /*!< Protected*/
#endif
  u8 CMSR;        /*!< Clock Master Status Register */
  u8 SWR;         /*!< Clock Master Switch Register */
  u8 SWCR;        /*!< Switch Control Register */
  u8 CKDIVR;      /*!< Clock Divider Register */
  u8 PCKEN1R;     /*!< Peripheral Clock Gating Register 1 */
  u8 CSSR;        /*!< Clock Security System Register */
  u8 CCOR;        /*!< Configurable Clock Output Register */
#ifdef HW_PLATFORM_TEST_CHIP
  u8 HSESTBR;  /*!< HSE QUARTZ STABILIZATION REGISTER    */
#endif
  u8 PCKEN2R;     /*!< Peripheral Clock Gating Register 2 */
  u8 HSEDIVCANR;  /*!< HSE Division factor for CAN Register */ /* TBD not in datasheet */
  u8 HSITRIMR;    /*!< HSI Calibration Trimmer Register */ /* TBD not in datasheet */
#ifndef HW_PLATFORM_TEST_CHIP
	u8 SWIMCLKDIVR; /*!< Swim Clock Divider Register */ /* TBD not in datasheet */
#endif
}
CLK_TypeDef;

/** @addtogroup CLK_Registers_Reset_Value
  * @{
  */
#define CLK_ICKR_RESET_VALUE        ((u8)0x01)
#define CLK_ECKR_RESET_VALUE        ((u8)0x00)
#ifdef  HW_PLATFORM_TEST_CHIP
#define CLK_PLLR_RESET_VALUE        ((u8)0x08) /* TBD to be remove in final release */
#define CLK_HSESTBR_RESET_VALUE     ((u8)0x00) /* TBD to be remove in final release */
#endif
#define CLK_CMSR_RESET_VALUE        ((u8)0xE1)
#define CLK_SWR_RESET_VALUE         ((u8)0xE1)
#define CLK_SWCR_RESET_VALUE        ((u8)0x00)
#define CLK_CKDIVR_RESET_VALUE      ((u8)0x18)
#define CLK_PCKEN1R_RESET_VALUE     ((u8)0xFF)
#define CLK_PCKEN2R_RESET_VALUE     ((u8)0xFF)
#define CLK_CSSR_RESET_VALUE        ((u8)0x00)
#define CLK_CCOR_RESET_VALUE        ((u8)0x00)
#define CLK_HSEDIVCANR_RESET_VALUE  ((u8)0x00)
#define	CLK_HSITRIMR_RESET_VALUE    ((u8)0x10) /*!< HSI Trimming reset value. */
#define CLK_SWIMCLKDIVR_RESET_VALUE ((u8)0x00)
/**
  * @}
  */

/** @addtogroup CLK_Registers_Bits_Definition
  * @{
  */

#define CLK_ICKR_SHW    ((u8)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
#define CLK_ICKR_LSIRDY ((u8)0x10) /*!< Low speed internal oscillator ready */
#define CLK_ICKR_LSIEN  ((u8)0x08) /*!< Low speed internal RC oscillator enable */
#define CLK_ICKR_FHW    ((u8)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
#define CLK_ICKR_HSIRDY ((u8)0x02) /*!< High speed internal RC oscillator ready */
#define CLK_ICKR_HSIEN  ((u8)0x01) /*!< High speed internal RC oscillator enable */

#ifdef  HW_PLATFORM_TEST_CHIP /* TBD to be remove in final release */
#define CLK_ECKR_LSERDY ((u8)0x10)
#define CLK_ECKR_LSEEN  ((u8)0x08)
#define CLK_ECKR_HSECNF ((u8)0x04)
#endif
#define CLK_ECKR_HSERDY ((u8)0x02) /*!< High speed external crystal oscillator ready */
#define CLK_ECKR_HSEON  ((u8)0x01) /*!< High speed external crystal oscillator enable */

#ifdef  HW_PLATFORM_TEST_CHIP /* TBD to be remove in final release */
#define CLK_PLLR_SPREADCTL ((u8)0x20) /*!< PLL spread control */
#define CLK_PLLR_SSCGCTL   ((u8)0x10) /*!< PLL sscg control */
#define CLK_PLLR_BYPASS    ((u8)0x08) /*!< PLL bypass */
#define CLK_PLLR_PLLREF    ((u8)0x04) /*!< PLL reference frequency */
#define CLK_PLLR_PLLRDY    ((u8)0x02) /*!< PLL locked-state flag */
#define CLK_PLLR_PLLON     ((u8)0x01) /*!< PLL oscillator on/off control */
#endif

#define CLK_CMSR_CKM    ((u8)0xFF) /*!< Clock master status bits */

#define CLK_SWR_SWI     ((u8)0xFF) /*!< Clock master selection bits */

#define CLK_SWCR_SWIF   ((u8)0x08) /*!< Clock switch interrupt flag */
#define CLK_SWCR_IEN    ((u8)0x04) /*!< Clock switch interrupt enable */
#define CLK_SWCR_EN     ((u8)0x02) /*!< Switch start/stop */
#define CLK_SWCR_SWBSY  ((u8)0x01) /*!< Switch busy */

#define CLK_CKDIVR_HSIDIV ((u8)0x18) /*!< High speed internal clock prescaler */
#define CLK_CKDIVR_CPUDIV ((u8)0x07) /*!< CPU clock prescaler */

#define CLK_PCKEN1R_TIM1    ((u8)0x80) /*!< Timer 1 clock enable */ /* TBD verify if correct timer */
#define CLK_PCKEN1R_TIM3    ((u8)0x40) /*!< Timer 3 clock enable */
#define CLK_PCKEN1R_TIM2    ((u8)0x20) /*!< Timer 2 clock enable */
#define CLK_PCKEN1R_TIM4    ((u8)0x10) /*!< Timer 4 clock enable */ /* TBD verify if correct timer */
#define CLK_PCKEN1R_LINUART ((u8)0x08) /*!< LINUART clock enable */
#define CLK_PCKEN1R_USART   ((u8)0x04) /*!< USART clock enable */
#define CLK_PCKEN1R_SPI     ((u8)0x02) /*!< SPI clock enable */
#define CLK_PCKEN1R_I2C     ((u8)0x01) /*!< I2C clock enable */

#define CLK_PCKEN2R_CAN ((u8)0x80) /*!< CAN clock enable */
#define CLK_PCKEN2R_ADC ((u8)0x08) /*!< ADC clock enable */
#define CLK_PCKEN2R_AWU ((u8)0x04) /*!< AWU clock enable */

#define CLK_CSSR_CSSD   ((u8)0x08) /*!< Clock security system detection */
#define CLK_CSSR_CSSDIE ((u8)0x04) /*!< Clock security system detection interrupt enable */
#define CLK_CSSR_AUX    ((u8)0x02) /*!< Auxiliary oscillator connected to master clock */
#define CLK_CSSR_CSSEN  ((u8)0x01) /*!< Clock security system enable */

#define CLK_CCOR_CCOBSY ((u8)0x40) /*!< Configurable clock output busy */
#define CLK_CCOR_CCORDY ((u8)0x20) /*!< Configurable clock output ready */
#define CLK_CCOR_CCOSEL ((u8)0x1E) /*!< Configurable clock output selection */
#define CLK_CCOR_CCOEN  ((u8)0x01) /*!< Configurable clock output enable */

#define CLK_HSEDIVCANR_CAN ((u8)0x0F) /*!< High speed external clock divider for CAN clock */ /* TBD not in datasheet */

#define CLK_HSITRIMR_HSITRIM ((u8)0x07) /*!< High speed internal oscillator trimmer */ /* TBD not in datasheet */

#define CLK_SWIMCLKDIVR_NSWIMCK0 ((u8)0x01) /*!< SWIM Clock Dividing Factor */ /* TBD not in datasheet */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief High End Timer (HTIM)
  */
typedef volatile struct HTIM_struct
{
  u8 CR1; /*control register 1   */
  u8 CR2; /*control register 2   */
  u8 SMCR; /*Synchro mode control register */
  u8 ETR; /* external trigger register */
  u8 IER; /*interrupt enable register*/
  u8 SR1; /*status register 1   */
  u8 SR2; /*status register 2   */
  u8 EGR; /*event generation register */
  u8 CCMR1; /*CC mode register 1      */
  u8 CCMR2; /*CC mode register 2      */
  u8 CCMR3; /*CC mode register 3      */
#ifdef HW_PLATFORM_CUT10
  u8 CCMR4; /*CC mode register 3      */
#endif  
  u8 CCER1; /*CC enable register 1     */
  u8 CCER2; /*CC enable register 2     */
  u8 CNTRH; /*counter high       */
  u8 CNTRL; /*counter low       */
  u8 PSCRH; /*prescaler high    */
  u8 PSCRL; /*prescaler low    */
  u8 ARRH; /*auto-reload register high  */
  u8 ARRL; /*auto-reload register low    */
  u8 RCR; /* Repetition Counter register */
  u8 CCR1H; /*capture/compare register 1 high   */
  u8 CCR1L; /*capture/compare register 1 low     */
  u8 CCR2H; /*capture/compare register 2 high   */
  u8 CCR2L; /*capture/compare register 2 low     */
  u8 CCR3H; /*capture/compare register 3 high    */
  u8 CCR3L; /*capture/compare register 3 low      */
#ifdef HW_PLATFORM_CUT10
  u8 CCR4H; /*capture/compare register 3 high    */
  u8 CCR4L; /*capture/compare register 3 low      */
#endif
  u8 BKR; /* Break Register */
  u8 DTR; /* dead-time register */
  u8 OISR; /* Output idle register */
}
HTIM_TypeDef;

/** @addtogroup HTIM_Registers_Reset_Value
  * @{
  */
#define HTIM_CR1_RESET_VALUE ((u8)0x00)
#define HTIM_CR2_RESET_VALUE ((u8)0x00)
#define HTIM_SMCR_RESET_VALUE ((u8)0x00)
#define HTIM_ETR_RESET_VALUE ((u8)0x00)
#define HTIM_IER_RESET_VALUE ((u8)0x00)
#define HTIM_SR1_RESET_VALUE ((u8)0x00)
#define HTIM_SR2_RESET_VALUE ((u8)0x00)
#define HTIM_EGR_RESET_VALUE ((u8)0x00)
#define HTIM_CCMR1_RESET_VALUE ((u8)0x00)
#define HTIM_CCMR2_RESET_VALUE ((u8)0x00)
#define HTIM_CCMR3_RESET_VALUE ((u8)0x00)
#ifdef HW_PLATFORM_CUT10
#define HTIM_CCMR4_RESET_VALUE ((u8)0x00)
#endif
#define HTIM_CCER1_RESET_VALUE ((u8)0x00)
#define HTIM_CCER2_RESET_VALUE ((u8)0x00)
#define HTIM_CNTRH_RESET_VALUE ((u8)0x00)
#define HTIM_CNTRL_RESET_VALUE ((u8)0x00)
#define HTIM_PSCH_RESET_VALUE ((u8)0x00)
#define HTIM_PSCL_RESET_VALUE ((u8)0x00)
#define HTIM_ARRH_RESET_VALUE ((u8)0xFF)
#define HTIM_ARRL_RESET_VALUE ((u8)0xFF)
#define HTIM_RCR_RESET_VALUE ((u8)0x00)
#define HTIM_CCR1H_RESET_VALUE ((u8)0x00)
#define HTIM_CCR1L_RESET_VALUE ((u8)0x00)
#define HTIM_CCR2H_RESET_VALUE ((u8)0x00)
#define HTIM_CCR2L_RESET_VALUE ((u8)0x00)
#define HTIM_CCR3H_RESET_VALUE ((u8)0x00)
#define HTIM_CCR3L_RESET_VALUE ((u8)0x00)
#ifdef HW_PLATFORM_CUT10
#define HTIM_CCR4H_RESET_VALUE ((u8)0x00)
#define HTIM_CCR4L_RESET_VALUE ((u8)0x00)
#endif
#define HTIM_BKR_RESET_VALUE ((u8)0x00)
#define HTIM_DTR_RESET_VALUE ((u8)0x00)
#define HTIM_OISR_RESET_VALUE ((u8)0x00)
/**
  * @}
  */

/** @addtogroup HTIM_Registers_Bits_Definition
  * @{
  */
#define HTIM_CR1_ARPE    ((u8)0x80) /*!< Auto-Reload Preload Enable Mask. */
#define HTIM_CR1_CMS     ((u8)0x60) /*!< Center-aligned Mode Selection Mask. */
#define HTIM_CR1_DIR     ((u8)0x10) /*!< Direction Mask. */
#define HTIM_CR1_OPM     ((u8)0x08) /*!< One Pulse Mode Mask. */
#define HTIM_CR1_URS     ((u8)0x04) /*!< Update Request Source Mask. */
#define HTIM_CR1_UDIS    ((u8)0x02) /*!< Update DIsable Mask. */
#define HTIM_CR1_CEN     ((u8)0x01) /*!< Counter Enable Mask. */

#define HTIM_CR2_TI1S 	  ((u8)0x80) /*!< TI1S Selection Mask. */
#define HTIM_CR2_Reserved ((u8)0x7A) /*!< Reserved Bit Mask. */
#define HTIM_CR2_CCUS 	  ((u8)0x04) /*!< Capture/Compare Control Update Selection Mask. */
#define HTIM_CR2_CCPC     ((u8)0x01) /*!< Capture/Compare Preloaded Control Mask. */

#define HTIM_SMCR_Reserved ((u8)0x88) /*!< Reserved Bit Mask. */
#define HTIM_SMCR_TS       ((u8)0x70) /*!< Trigger Selection Mask. */
#define HTIM_SMCR_SMS      ((u8)0x07) /*!< Slave Mode Selection Mask. */

#define HTIM_ETR_ETP       ((u8)0x80) /*!< External Trigger Polarity Mask. */
#define HTIM_ETR_ECE       ((u8)0x40) /*!< External Clock Enable Mask. */
#define HTIM_ETR_ETPS      ((u8)0x30) /*!< External Trigger Prescaler Mask. */
#define HTIM_ETR_ETF       ((u8)0x0F) /*!< External Trigger Filter Mask. */

#define HTIM_IER_BIE       ((u8)0x80) /*!< Break Interrupt Enable Mask. */
#define HTIM_IER_TIE       ((u8)0x40) /*!< Trigger Interrupt Enable Mask. */
#define HTIM_IER_CCUIE     ((u8)0x20) /*!<  CC-Update Interrupt Enable Mask.*/