s3c44b0x.h

Vxworks_Bsp_S344b0x Source

/* s3c44b0x.h - header for Samsung s3c44b0x with ARM7 core */

/* Copyright 2004-2008 Amine. */

#ifndef __INCs3c44b0xh
#define __INCs3c44b0xh

#ifdef __cplusplus
extern "C" {
#endif

/* System */
#define S3C44B0X_SYSCFG             (0x1c00000)
                            
/* Cache */                 
#define S3C44B0X_NCACHBE0           (0x1c00004)
#define S3C44B0X_NCACHBE1           (0x1c00008)
                            
/* Bus control */           
#define S3C44B0X_SBUSCON            (0x1c40000)
    
/* Memory control */
#define S3C44B0X_BWSCON             (0x1c80000)
#define S3C44B0X_BANKCON0           (0x1c80004)
#define S3C44B0X_BANKCON1           (0x1c80008)
#define S3C44B0X_BANKCON2           (0x1c8000c)
#define S3C44B0X_BANKCON3           (0x1c80010)
#define S3C44B0X_BANKCON4           (0x1c80014)
#define S3C44B0X_BANKCON5           (0x1c80018)
#define S3C44B0X_BANKCON6           (0x1c8001c)
#define S3C44B0X_BANKCON7           (0x1c80020)
#define S3C44B0X_REFRESH            (0x1c80024)
#define S3C44B0X_BANKSIZE           (0x1c80028)
#define S3C44B0X_MRSRB6             (0x1c8002c)
#define S3C44B0X_MRSRB7             (0x1c80030)

/* Clock & Power management */
#define S3C44B0X_PLLCON          	(0x1d80000)
#define S3C44B0X_CLKCON           	(0x1d80004)
#define S3C44B0X_CLKSLOW          	(0x1d80008)
#define S3C44B0X_LOCKTIME         	(0x1d8000c)

/* Interrupt */           
#define S3C44B0X_INTCON           	(0x1e00000)
#define S3C44B0X_INTPND           	(0x1e00004)
#define S3C44B0X_INTMOD           	(0x1e00008)
#define S3C44B0X_INTMSK           	(0x1e0000c)

#define S3C44B0X_INTNUMLEVELS       26
#define S3C44B0X_INTMASK_VAL        0x03ffffff
#define SNGKS32C_INTMODEIRQ         0x00

#define S3C44B0X_INTENB         	S3C44B0X_INTMSK
#define S3C44B0X_INTDIS         	S3C44B0X_INTMSK
                          
#define S3C44B0X_I_PSLV           	(0x1e00010)
#define S3C44B0X_I_PMST           	(0x1e00014)
#define S3C44B0X_I_CSLV           	(0x1e00018)
#define S3C44B0X_I_CMST           	(0x1e0001c)
#define S3C44B0X_I_ISPR           	(0x1e00020)
#define S3C44B0X_I_ISPC           	(0x1e00024)
                          
#define S3C44B0X_F_ISPR           	(0x1e00038)
#define S3C44B0X_F_ISPC           	(0x1e0003c)

/* WATCHDOG */            
#define S3C44B0X_WTCON            	(0x1d30000)
#define S3C44B0X_WTDAT            	(0x1d30004)
#define S3C44B0X_WTCNT            	(0x1d30008)

/* definitions for the KS32C50100 UART */
#define SERIAL_A_BASE_ADR       	(0x1d00000)/* UART A base address */
#define SERIAL_B_BASE_ADR       	(0x1d04000)/* UART B base address */


/* I/O PORT */          
#if 0
#define S3C44B0X_PCONA            	(0x1d20000)
#define S3C44B0X_PDATA            	(0x1d20004)
                        
#define S3C44B0X_PCONB            	(0x1d20008)
#define S3C44B0X_PDATB            	(0x1d2000c)
                        
#define S3C44B0X_PCONC            	(0x1d20010)
#define S3C44B0X_PDATC            	(0x1d20014)
#define S3C44B0X_PUPC             	(0x1d20018)
                        
#define S3C44B0X_PCOND            	(0x1d2001c)
#define S3C44B0X_PDATD            	(0x1d20020)
#define S3C44B0X_PUPD             	(0x1d20024)
                        
#define S3C44B0X_PCONE            	(0x1d20028)
#define S3C44B0X_PDATE            	(0x1d2002c)
#define S3C44B0X_PUPE             	(0x1d20030)
                          
#define S3C44B0X_PCONF            	(0x1d20034)
#define S3C44B0X_PDATF            	(0x1d20038)
#define S3C44B0X_PUPF             	(0x1d2003c)
                          
#define S3C44B0X_PCONG            	(0x1d20040)
#define S3C44B0X_PDATG            	(0x1d20044)
#define S3C44B0X_PUPG             	(0x1d20048)
                          
#define S3C44B0X_SPUCR            	(0x1d2004c)
#define S3C44B0X_EXTINT           	(0x1d20050)
#define S3C44B0X_EXTINTPND        	(0x1d20054)
#endif
/* I/O PORT */          
#define rPCONA            (*(volatile unsigned *)0x1d20000)
#define rPDATA            (*(volatile unsigned *)0x1d20004)
                        
#define rPCONB            (*(volatile unsigned *)0x1d20008)
#define rPDATB            (*(volatile unsigned *)0x1d2000c)
                        
#define rPCONC            (*(volatile unsigned *)0x1d20010)
#define rPDATC            (*(volatile unsigned *)0x1d20014)
#define rPUPC             (*(volatile unsigned *)0x1d20018)
                        
#define rPCOND            (*(volatile unsigned *)0x1d2001c)
#define rPDATD            (*(volatile unsigned *)0x1d20020)
#define rPUPD             (*(volatile unsigned *)0x1d20024)
                        
#define rPCONE            (*(volatile unsigned *)0x1d20028)
#define rPDATE            (*(volatile unsigned *)0x1d2002c)
#define rPUPE             (*(volatile unsigned *)0x1d20030)
                          
#define rPCONF            (*(volatile unsigned *)0x1d20034)
#define rPDATF            (*(volatile unsigned *)0x1d20038)
#define rPUPF             (*(volatile unsigned *)0x1d2003c)
                          
#define rPCONG            (*(volatile unsigned *)0x1d20040)
#define rPDATG            (*(volatile unsigned *)0x1d20044)
#define rPUPG             (*(volatile unsigned *)0x1d20048)
                          
#define rSPUCR            (*(volatile unsigned *)0x1d2004c)
#define rEXTINT           (*(volatile unsigned *)0x1d20050)
#define rEXTINTPND        (*(volatile unsigned *)0x1d20054)

#define NETBASE           ((volatile unsigned char  *)(0x60a0000))
#define CPLDREG1         ((volatile unsigned  char  *)(0xa200000))
#define CPLDREG2         ((volatile unsigned  char  *)(0xa210000))
#define CPLDREG3         ((volatile unsigned  char  *)(0xa220000))
#define CPLDREG4         ((volatile unsigned  char  *)(0xa230000))
#define CPLDREG5         ((volatile unsigned  char  *)(0xa240000))

/*#define SNGKS32C_EXTACON0      (ASIC_BASE+0x3008)
#define SNGKS32C_EXTACON1      (ASIC_BASE+0x300c)
#define SNGKS32C_EXTDBWTH      (ASIC_BASE+0x3010)*/
/*#define SNGKS32C_REFEXTCON     (ASIC_BASE+0x303c)*/

/* controller registers */
/*#define SNGKS32C_INTOFFSET     (ASIC_BASE+0x4024)
#define SNGKS32C_INTPENDTST    (ASIC_BASE+0x402c)*/


/*#define SNGKS32C_INT_DISABLE        0x1fffff
*/

/*#define SNGKS32C_INTPRI0        (ASIC_BASE+0x400C)
#define SNGKS32C_INTPRI1        (ASIC_BASE+0x4010)
#define SNGKS32C_INTPRI2        (ASIC_BASE+0x4014)
#define SNGKS32C_INTPRI3        (ASIC_BASE+0x4018)
#define SNGKS32C_INTPRI4        (ASIC_BASE+0x401C)
#define SNGKS32C_INTPRI5        (ASIC_BASE+0x4020)

#define SNGKS32C_INTOSET_FIQ    (ASIC_BASE+0x4030)
#define SNGKS32C_INTOSET_IRQ    (ASIC_BASE+0x4034)*/

 /* I/O Port Interface  */

/*#define SNGKS32C_IOPMOD         (ASIC_BASE+0x5000)
#define SNGKS32C_IOPCON         (ASIC_BASE+0x5004)
#define SNGKS32C_IOPDATA        (ASIC_BASE+0x5008)*/

/* IIC Registers */
/*#define  SNGKS32C_IICCON        (ASIC_BASE+0xf000)
#define  SNGKS32C_IICBUF        (ASIC_BASE+0xf004)
#define  SNGKS32C_IICPS         (ASIC_BASE+0xf008)
#define  SNGKS32C_IICCNT        (ASIC_BASE+0xf00c)*/

#ifdef __cplusplus
}
#endif

#endif /* __INCs3c44b0xh */