ppc860sio.h

PowerPC与PC微机串行通信

/* Copyright 1984-1998 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,07jan99,cn   fixed properly SPR# 22503 and SPR# 24296.
01f,22oct98,cn   added missing parenthesis in some defines (SPR# 22503).
01e,13apr98,map  moved SCC device definitions to ../multi/ppc860Cpm.h
                 renamed SCC_DEV to SCC_UART_DEV
01d,26mar98,map  added SMC, SCC, PIP defines.
01c,24may96,tpr  changed statusMode from VINT16 to VUINT16.
01b,22apr96,cah  change definitions to be offsets from a known #define
		 constant, rather than from a run-time IMMR register value.
		 Changes are required in sysSerial.c for this as well.
01a,11apr96,cah	 created.
*/

/*
 * This file contains constants for the Motorola MPC860 PowerPC
 * microcontroller chip.
 */

#ifndef __INCppc860Sioh
#define __INCppc860Sioh

#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASMLANGUAGE

#include "sioLib.h"
#include "drv/multi/ppc860Cpm.h"
#include "drv/multi/ppc860Siu.h"

/* device and channel structures */

/* 
 * The PPC860SMC_CHAN structure defines a serial I/O channel which
 * describes the (TBD) registers for a given channel. 
 * Also the various SIO driver functions ( ioctl, txStarup, callbackInstall,
 * pollInput, polloutput ) that this channel could utilize are declared 
 * here.
 */


/*  roughly things copied in structure form from multi/m68360.h    */

/* MPC860 Dual Ported Ram addresses */

#define PPC860_DPR_SCC1(dprbase)     ((VINT32 *) ((dprbase) + 0x1c00))
#define PPC860_DPR_I2C(dprbase)      ((VINT32 *) ((dprbase) + 0x1c80))
#define PPC860_DPR_MISC(dprbase)     ((VINT32 *) ((dprbase) + 0x1cb0))
#define PPC860_DPR_IDMA1(dprbase)    ((VINT32 *) ((dprbase) + 0x1cc0))
#define PPC860_DPR_SCC2(dprbase)     ((VINT32 *) ((dprbase) + 0x1d00))
#define PPC860_DPR_SPI(dprbase)      ((VINT32 *) ((dprbase) + 0x1d80))
#define PPC860_DPR_TMR(dprbase)      ((VINT32 *) ((dprbase) + 0x1db0))
#define PPC860_DPR_IDMA2(dprbase)    ((VINT32 *) ((dprbase) + 0x1dc0))
#define PPC860_DPR_SCC3(dprbase)     ((VINT32 *) ((dprbase) + 0x1e00))
#define PPC860_DPR_SMC1(dprbase)     ((VINT32 *) ((dprbase) + 0x1e80))
#define PPC860_DPR_DSP1(dprbase)     ((VINT32 *) ((dprbase) + 0x1ec0))
#define PPC860_DPR_SCC4(dprbase)     ((VINT32 *) ((dprbase) + 0x1f00))
#define PPC860_DPR_SMC2(dprbase)     ((VINT32 *) ((dprbase) + 0x1f80))
#define PPC860_DPR_DSP2(dprbase)     ((VINT32 *) ((dprbase) + 0x1fc0))

/*
 * dual-ported parameter RAM SMC offsets                     
 * access these with SMC_RBASE(base_dpram_addr_of_this_SMC1) 
 * base_dpram_addr_of_this_SMC1 == PPC860_DPR_SMC1(dprbase)  
 * or == PPC860_DPR_SMC2(dprbase)                            
 */
#define SMC_RBASE(base)   ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
#define SMC_TBASE(base)   ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
#define SMC_RFCR(base)    ((VINT8  *) ((base) + 0x04)) /* Rx Function Code */
#define SMC_TFCR(base)    ((VINT8  *) ((base) + 0x05)) /* Tx Function Code */
#define SMC_MRBLR(base)   ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
#define SMC_RSTATE(base)  ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
#define SMC_RBPTR(base)   ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
#define SMC_TSTATE(base)  ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
#define SMC_TBPTR(base)   ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
#define SMC_MAX_IDL(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
#define SMC_IDLC(base)    ((VINT16 *) ((base) + 0x2A)) /* Temp Idle counter */
#define SMC_BRKLN(base)   ((VINT16 *) ((base) + 0x2C)) /* Last Rx Break length*/
#define SMC_BRKEC(base)   ((VINT16 *) ((base) + 0x2E)) /* Rx Brk Cond counter */
#define SMC_BRKCR(base)   ((VINT16 *) ((base) + 0x30)) /* Break Count reg (Tx)*/
#define SMC_RMASK(base)   ((VINT16 *) ((base) + 0x32)) /* Temp bit mask */

/* dual ported parameter RAM PIP offsets */
                           
#define PIP_RBASE(base)   ((VINT16 *)((base) + 0x00)) /* Rx Buff Descr Base */
#define PIP_TBASE(base)   ((VINT16 *)((base) + 0x01)) /* Tx Buff Descr Base */
#define PIP_CFCR(base)    ((VINT8  *)((base) + 0x04)) /* Cent. Function Code */
#define PIP_SMASK(base)   ((VINT8  *)((base) + 0x05)) /* Status mask */

/* 
 * dual-ported parameter RAM SCC offsets                       
 * access these with SCC_RBASE(base_dpram_addr_of_this_SCC1)    
 * base_dpram_addr_of_this_SCC1 == PPC860_DPR_SCC1(dprbase)    
 * or == PPC860_DPR_SCC1(dprbase)                              
 */

#define SCC_RBASE(base)   ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
#define SCC_TBASE(base)   ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
#define SCC_RFCR(base)    ((VINT8  *) ((base) + 0x04)) /* Rx Function Code */
#define SCC_TFCR(base)    ((VINT8  *) ((base) + 0x05)) /* Tx Function Code */
#define SCC_MRBLR(base)   ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
#define SCC_RSTATE(base)  ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
#define SCC_RBPTR(base)   ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
#define SCC_TSTATE(base)  ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
#define SCC_TBPTR(base)   ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
#define SCC_RCRC(base)    ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
#define SCC_TCRC(base)    ((VINT16 *) ((base) + 0x2C)) /* Max Idle characters */
#define SCC_MAX_IDL(base) ((VINT16 *) ((base) + 0x38)) /* Max Idle characters */
#define SCC_IDLC(base)    ((VINT16 *) ((base) + 0x3A)) /* Temp Idle counter */
#define SCC_BRKCR(base)   ((VINT16 *) ((base) + 0x3C)) /* Break Count Reg (Tx)*/
#define SCC_PAREC(base)   ((VINT16 *) ((base) + 0x3E)) /* Rx Parity Err Cnt */
#define SCC_FRMEC(base)   ((VINT16 *) ((base) + 0x40)) /* Rx Frame Err Cnt */
#define SCC_NOSEC(base)   ((VINT16 *) ((base) + 0x42)) /* Receive Noise Cnt */

/*
 * dual-ported parameter RAM I2C offsets
 * access these with I2C_RPBASE(base_dpram_addr_of_I2C)
 */

#define I2C_RPBASE(base)  ((VINT16 *) ((char *)base + 0x2C))



typedef struct          /* SMC_BUF */
    {
    VUINT16	statusMode;             /* status and control */
    VINT16      dataLength;             /* length of data buffer in bytes */
    u_char *    dataPointer;            /* points to data buffer */
    } SMC_BUF;

typedef struct          /* SMC_PARAM */
    {		                /* offset description*/
    VINT16      rbase;          /* 00 Rx buffer descriptor base address */
    VINT16      tbase;          /* 02 Tx buffer descriptor base address */
    VINT8       rfcr;           /* 04 Rx function code */
    VINT8       tfcr;           /* 05 Tx function code */
    VINT16      mrblr;          /* 06 maximum receive buffer length */
    VINT32      rstate;         /* 08 Rx internal state */
    VINT32      res1;           /* 0C Rx internal data pointer */
    VINT16      rbptr;          /* 10 Rx buffer descriptor pointer */
    VINT16      res2;           /* 12 reserved/internal */
    VINT32      res3;           /* 14 reserved/internal */
    VINT32      tstate;         /* 18 Tx internal state */
    VINT32      res4;           /* 1C reserved/internal */
    VINT16      tbptr;          /* 20 Tx buffer descriptor pointer */
    VINT16      res5;           /* 22 reserved/internal */
    VINT32      res6;           /* 24 reserved/internal */
    VINT16      maxidl;         /* 28 Maximum idle characters */
    VINT16      idlc;           /* 2A temporary idle counter */
    VINT16      brkln;          /* 2C last recv break length */
    VINT16      brkec;          /* 2E recv break condition counter */
    VINT16      brkcr;          /* 30 xmit break count register */
    VINT16      r_mask;         /* 32 temporary bit mask */
    } SMC_PARAM;

typedef struct          /* SMC */
    {
    SMC_PARAM   param;                  /* SMC parameters */
    } SMC;

typedef struct          /* SMC_REG */
    {
    VINT16      smcmr;                  /* SMC Mode register */
    VINT8	res1[2];		/* reserved */
    VINT8       smce;                   /* SMC Event register */
    VINT8	res2[3];		/* reserved */
    VINT8       smcm;                   /* SMC Mask register */
    } SMC_REG;

/* SMC device descriptor */

typedef struct          /* SMC_DEV */
    {
    int                 smcNum;         /* number of SMC device (1 or 2)*/
    int                 txBdNum;        /* number of transmit buf descriptors */
    int                 rxBdNum;        /* number of receive buf descriptors */
    SMC_BUF *           txBdBase;       /* transmit BD base address */
    SMC_BUF *           rxBdBase;       /* receive BD base address */
    u_char *            txBufBase;      /* transmit buffer base address */
    u_char *            rxBufBase;      /* receive buffer base address */
    VINT32              txBufSize;      /* transmit buffer size */
    VINT32              rxBufSize;      /* receive buffer size */
    int                 txBdNext;       /* next transmit BD to fill */
    int                 rxBdNext;       /* next receive BD to read */
    volatile SMC *      pSmc;           /* SMC parameter RAM. Must point */
					/* at DPRAM area for SMC1 or SMC2 */
    volatile SMC_REG *  pSmcReg;        /* SMC registers must point at */
					/* SMCMR1 or SMCMR2 */
    VINT32              intMask;        /* interrupt acknowledge mask */
    } SMC_DEV;

/* SCC device descriptor */

typedef struct          /* SCC_UART_DEV */
    {
    int 		sccNum;		/* number of SCC device */
    int 		txBdNum;	/* number of transmit buf descriptors */
    int 		rxBdNum;	/* number of receive buf descriptors */
    SCC_BUF * 		txBdBase;	/* transmit BD base address */
    SCC_BUF * 		rxBdBase;	/* receive BD base address */
    u_char * 		txBufBase;	/* transmit buffer base address */
    u_char *		rxBufBase;	/* receive buffer base address */
    VINT32 		txBufSize;	/* transmit buffer size */
    VINT32 		rxBufSize;	/* receive buffer size */
    int			txBdNext;	/* next transmit BD to fill */
    int			rxBdNext;	/* next receive BD to read */
    volatile SCC *	pScc;		/* SCC parameter RAM */
    volatile SCC_REG *	pSccReg;	/* SCC registers */
    VINT32		intMask;	/* interrupt acknowledge mask */
    } SCC_UART_DEV;

typedef struct          	/* I2C_PARAM */
    {				/* offset description */
    VINT16 	rbase;		/* 00 Rx buffer descriptors base address */
    VINT16 	tbase;		/* 02 Tx buffer descriptors base address */
    VINT8 	rfcr;		/* 04 Rx function code */
    VINT8 	tfcr;		/* 05 Tx function code */
    VINT16 	mrblr;		/* 06 maximum receive buffer length */
    VINT32 	ris;		/* 08 Rx internal state */
    VINT32 	ridp;		/* 0c Rx internal data pointer */
    VINT16 	rbptr;		/* 10 Rx buffer descriptor pointer */
    VINT16 	ribc;		/* 12 Rx internal byte count */
    VINT32 	rt;		/* 14 Rx temp */
    VINT32 	tis;		/* 18 Tx internal state */
    VINT32 	tidp;		/* 1c Tx internal data pointer */
    VINT16 	tbptr;		/* 20 Tx buffer descriptor pointer */
    VINT16 	tibc;		/* 22 Tx internal byte count */
    VINT32 	tt;		/* 24 Tx temp */
    VINT32 	notused;	/* 28 not used */
    VINT16 	rpbase;		/* 2c relocatable parameter RAM base */
    VINT16 	reserved;	/* 2e reserved */
    } I2C_PARAM;

/* standard dual-mode serial driver header structure follows      */

typedef struct ppc860_chan	/* PPC860SMC_CHAN */
    {
    /* always goes first */
    SIO_DRV_FUNCS	*pDrvFuncs;	/* driver functions */
    
    /* callbacks */

    STATUS	(*getTxChar)();	/* pointer to a xmitr function */
    STATUS	(*putRcvChar)();/* pointer to a recvr function */
    void *	getTxArg;
    void *	putRcvArg;

    VINT16              int_vec;        /* interrupt vector number */
    VINT16              channelMode;    /* SIO_MODE                */
    int                 baudRate;
    int                 clockRate;      /* CPU clock frequency (Hz) */
    int                 bgrNum;         /* number of BRG being used */
    VINT32 *            pBaud;          /* BRG registers */
    VINT32              regBase;        /* register/DPR base address */
    SMC_DEV             uart;           /* UART SCC device */
    } PPC860SMC_CHAN;


/* serial procedures */
IMPORT	void	ppc860DevInit		(PPC860SMC_CHAN *);
IMPORT	void	ppc860Int		(PPC860SMC_CHAN *);
IMPORT	void	ppc800DevInit		(PPC860SMC_CHAN *);
IMPORT	void	ppc800Int		(PPC860SMC_CHAN *);

/*  standard dual-mode serial driver header structure follows - SCC */

typedef struct ppc860Scc_chan	/* PPC860SCC_CHAN */
    {
    /* always goes first */

    SIO_DRV_FUNCS	*pDrvFuncs;	/* driver functions */
    
    /* callbacks */

    STATUS	(*getTxChar)();	/* pointer to a xmitr function */
    STATUS	(*putRcvChar)();/* pointer to a recvr function */
    void *	getTxArg;
    void *	putRcvArg;

    VINT16              int_vec;        /* interrupt vector number */
    VINT16              channelMode;    /* SIO_MODE                */
    int                 baudRate;
    int                 clockRate;      /* CPU clock frequency (Hz) */
    int                 bgrNum;         /* number of BRG being used */
    VINT32 *            pBaud;          /* BRG registers */
    VINT32              regBase;        /* register/DPR base address */
    SCC_UART_DEV        uart;           /* UART SCC device */
    } PPC860SCC_CHAN;

/* function declarations */

IMPORT	void	ppc860SccInt		(PPC860SCC_CHAN *);
IMPORT	void	ppc860SccDevInit	(PPC860SCC_CHAN *);

/* channels */

#define PPC860_CHANNEL_A	0
#define PPC860_CHANNEL_B	1

#define PPC860SMC_N_CHANS    2	/* number of serial channels on chip */

/* SIO -- mpc860 serial channel chip -- register definitions */

/* Buffer Descriptor Pointer Definitions */

/* Receive BD status bits 16-bit value */

#define BD_RX_EMPTY_BIT		0x8000	/* buffer is empty */
#define BD_RX_WRAP_BIT		0x2000	/* last BD in chain */
#define BD_RX_INTERRUPT_BIT	0x1000	/* set interrupt when filled */
#define BD_RX_CON_MODE_BIT	0x0200	/* Continuous Mode bit */
#define BD_RX_IDLE_CLOSE_BIT	0x0100	/* Close on IDLE recv bit */
#define BD_RX_BREAK_CLOSE_BIT	0x0020	/* Close on break recv bit */
#define BD_RX_FRAME_CLOSE_BIT	0x0010	/* Close on frame error bit */
#define BD_RX_PARITY_ERROR_BIT	0x0008	/* Parity error in last byte */
#define BD_RX_OVERRUN_ERROR_BIT	0x0002	/* Overrun occurred */

/* Transmit BD status bits 16-bit value */

#define BD_TX_READY_BIT		0x8000	/* Transmit ready/busy bit */
#define BD_TX_WRAP_BIT		0x2000	/* last BD in chain */
#define BD_TX_INTERRUPT_BIT	0x1000	/* set interrupt when emptied */
#define BD_TX_CON_MODE_BIT	0x0200	/* Continuous Mode bit */
#define BD_TX_PREAMBLE_BIT	0x0100	/* send preamble sequence */

#define BD_STATUS_OFFSET	0x00	/* two bytes */
#define BD_DATA_LENGTH_OFFSET	0x02	/* two bytes */
#define	BD_BUF_POINTER_OFFSET	0x04	/* four bytes */

/*
 * MPC860 internal register/memory map (section 17 of prelim. spec)
 * note that these are offsets from the value stored in the IMMR
 * register, which is in the PowerPC special register address space
 * at register number 638
 */

/**** SIU module configuration ***/
#define MPC860_SIUMCR(base)	((VINT32 *) ((base) + 0x00))
/**** System Protection Control ***/