ppc860cpm.h

PowerPC与PC微机串行通信

#define SCC_GSMRL_ENR		0x00000020	/* enable receiver */
#define SCC_GSMRL_LOOPBACK	0x00000040	/* local loopback mode */
#define SCC_GSMRL_ECHO		0x00000080	/* automatic echo mode */
#define SCC_GSMRL_TENC		0x00000700	/* transmitter encoding method*/
#define SCC_GSMRL_RENC		0x00003800	/* receiver encoding method */
#define SCC_GSMRL_RDCR_X8	0x00004000	/* receive DPLL clock x8 */
#define SCC_GSMRL_RDCR_X16	0x00008000	/* receive DPLL clock x16 */
#define SCC_GSMRL_RDCR_X32	0x0000c000	/* receive DPLL clock x32 */
#define SCC_GSMRL_TDCR_X8	0x00010000	/* transmit DPLL clock x8 */
#define SCC_GSMRL_TDCR_X16	0x00020000	/* transmit DPLL clock x16 */
#define SCC_GSMRL_TDCR_X32	0x00030000	/* transmit DPLL clock x32 */
#define SCC_GSMRL_TEND		0x00040000	/* transmitter frame ending */
#define SCC_GSMRL_TPP_00	0x00180000	/* Tx preamble pattern = 00 */
#define SCC_GSMRL_TPP_10	0x00080000	/* Tx preamble pattern = 10 */
#define SCC_GSMRL_TPP_01	0x00100000	/* Tx preamble pattern = 01 */
#define SCC_GSMRL_TPP_11	0x00180000	/* Tx preamble pattern = 11 */
#define SCC_GSMRL_TPL_NONE	0x00000000	/* no Tx preamble (default) */
#define SCC_GSMRL_TPL_8		0x00200000	/* Tx preamble = 1 byte */
#define SCC_GSMRL_TPL_16	0x00400000	/* Tx preamble = 2 bytes */
#define SCC_GSMRL_TPL_32	0x00600000	/* Tx preamble = 4 bytes */
#define SCC_GSMRL_TPL_48	0x00800000	/* Tx preamble = 6 bytes */
#define SCC_GSMRL_TPL_64	0x00a00000	/* Tx preamble = 8 bytes */
#define SCC_GSMRL_TPL_128	0x00c00000	/* Tx preamble = 16 bytes */
#define SCC_GSMRL_TINV		0x01000000	/* DPLL transmit input invert */
#define SCC_GSMRL_RINV		0x02000000	/* DPLL receive input invert */
#define SCC_GSMRL_TSNC		0x0c000000	/* transmit sense */
#define SCC_GSMRL_TCI		0x10000000	/* transmit clock invert */
#define SCC_GSMRL_EDGE		0x60000000	/* adjustment edge +/- */

#define SCC_GSMRH_RSYN		0x00000001	/* receive sync timing*/
#define SCC_GSMRH_RTSM		0x00000002	/* RTS* mode */
#define SCC_GSMRH_SYNL		0x0000000c	/* sync length */
#define SCC_GSMRH_TXSY		0x00000010	/* transmitter/receiver sync */
#define SCC_GSMRH_RFW		0x00000020	/* Rx FIFO width */
#define SCC_GSMRH_TFL		0x00000040	/* transmit FIFO length */
#define SCC_GSMRH_CTSS		0x00000080	/* CTS* sampling */
#define SCC_GSMRH_CDS		0x00000100	/* CD* sampling */
#define SCC_GSMRH_CTSP		0x00000200	/* CTS* pulse */
#define SCC_GSMRH_CDP		0x00000400	/* CD* pulse */
#define SCC_GSMRH_TTX		0x00000800	/* transparent transmitter */
#define SCC_GSMRH_TRX		0x00001000	/* transparent receiver */
#define SCC_GSMRH_REVD		0x00002000	/* reverse data */
#define SCC_GSMRH_TCRC		0x0000c000	/* transparent CRC */
#define SCC_GSMRH_GDE		0x00010000	/* glitch detect enable */

/* SCC UART protocol specific parameters */

typedef struct		/* SCC_UART_PROTO */
    {
    UINT32	res1;			/* reserved */
    UINT32	res2;			/* reserved */
    UINT16	maxIdl;			/* maximum idle characters */
    UINT16	idlc;			/* temporary idle counter */
    UINT16	brkcr;			/* break count register (transmit) */
    UINT16	parec;			/* receive parity error counter */
    UINT16	frmer;			/* receive framing error counter */
    UINT16	nosec;			/* receive noise counter */
    UINT16	brkec;			/* receive break condition counter */
    UINT16	brkln;			/* last received break length */
    UINT16	uaddr1;			/* uart address character 1 */
    UINT16	uaddr2;			/* uart address character 2 */
    UINT16	rtemp;			/* temp storage */
    UINT16	toseq;			/* transmit out-of-sequence character */
    UINT16	character1;		/* control character 1 */
    UINT16	character2;		/* control character 2 */
    UINT16	character3;		/* control character 3 */
    UINT16	character4;		/* control character 4 */
    UINT16	character5;		/* control character 5 */
    UINT16	character6;		/* control character 6 */
    UINT16	character7;		/* control character 7 */
    UINT16	character8;		/* control character 8 */
    UINT16	rccm;			/* receive control character mask */
    UINT16	rccr;			/* receive control character register */
    UINT16	rlbc;			/* receive last break character */
    } SCC_UART_PROTO;

/* SCC UART Protocol Specific Mode Register definitions */

#define SCC_UART_PSMR_TPM_ODD	0x0000		/* odd parity mode (Tx) */
#define SCC_UART_PSMR_TPM_LOW	0x0001		/* low parity mode (Tx) */
#define SCC_UART_PSMR_TPM_EVEN	0x0002		/* even parity mode (Tx) */
#define SCC_UART_PSMR_TPM_HIGH	0x0003		/* high parity mode (Tx) */
#define SCC_UART_PSMR_RPM_ODD	0x0000		/* odd parity mode (Rx) */
#define SCC_UART_PSMR_RPM_LOW	0x0004		/* low parity mode (Rx) */
#define SCC_UART_PSMR_RPM_EVEN	0x0008		/* even parity mode (Rx) */
#define SCC_UART_PSMR_RPM_HIGH	0x000c		/* high parity mode (Rx) */
#define SCC_UART_PSMR_PEN	0x0010		/* parity enable */
#define SCC_UART_PSMR_DRT	0x0040		/* disable Rx while Tx */
#define SCC_UART_PSMR_SYN	0x0080		/* synchronous mode */
#define SCC_UART_PSMR_RZS	0x0100		/* receive zero stop bits */
#define SCC_UART_PSMR_FRZ	0x0200		/* freeze transmission */
#define SCC_UART_PSMR_UM_NML	0x0000		/* noraml UART operation */
#define SCC_UART_PSMR_UM_MULT_M	0x0400		/* multidrop non-auto mode */
#define SCC_UART_PSMR_UM_MULT_A	0x0c00		/* multidrop automatic mode */
#define SCC_UART_PSMR_CL_5BIT	0x0000		/* 5 bit character length */
#define SCC_UART_PSMR_CL_6BIT	0x1000		/* 6 bit character length */
#define SCC_UART_PSMR_CL_7BIT	0x2000		/* 7 bit character length */
#define SCC_UART_PSMR_CL_8BIT	0x3000		/* 8 bit character length */
#define SCC_UART_PSMR_SL	0x4000		/* 1 or 2 bit stop length */
#define SCC_UART_PSMR_FLC	0x8000		/* flow control */
	
/* SCC UART Event and Mask Register definitions */

#define SCC_UART_SCCX_RX 	0x0001		/* buffer received */
#define SCC_UART_SCCX_TX 	0x0002		/* buffer transmitted */
#define SCC_UART_SCCX_BSY 	0x0004		/* busy condition */
#define SCC_UART_SCCX_CCR 	0x0008		/* control character received */
#define SCC_UART_SCCX_BRK_S 	0x0020	 	/* break start */
#define SCC_UART_SCCX_BRK_E 	0x0040		/* break end */
#define SCC_UART_SCCX_GRA 	0x0080		/* graceful stop complete */
#define SCC_UART_SCCX_IDL	0x0100		/* idle sequence stat changed */
#define SCC_UART_SCCX_AB  	0x0200		/* autobaud lock */
#define SCC_UART_SCCX_GL_T 	0x0800		/* glitch on Tx */
#define SCC_UART_SCCX_GL_R 	0x1000		/* glitch on Rx */

/* SCC UART Receive Buffer Descriptor definitions */

#define SCC_UART_RX_BD_CD	0x0001		/* carrier detect loss */
#define SCC_UART_RX_BD_OV	0x0002		/* receiver overrun */
#define SCC_UART_RX_BD_PR	0x0008		/* parity error */
#define SCC_UART_RX_BD_FR	0x0010		/* framing error */
#define SCC_UART_RX_BD_BR	0x0020		/* break received */
#define SCC_UART_RX_BD_AM	0x0080		/* address match */
#define SCC_UART_RX_BD_ID	0x0100		/* buf closed on IDLES */
#define SCC_UART_RX_BD_CM	0x0200		/* continous mode */
#define SCC_UART_RX_BD_ADDR	0x0400		/* buffer contains address */
#define SCC_UART_RX_BD_CNT	0x0800		/* control character */
#define SCC_UART_RX_BD_INT	0x1000		/* interrupt generated */
#define SCC_UART_RX_BD_WRAP	0x2000		/* wrap back to first BD */
#define SCC_UART_RX_BD_EMPTY	0x8000		/* buffer is empty */

/* SCC UART Transmit Buffer Descriptor definitions */

#define SCC_UART_TX_BD_CT	0x0001		/* cts was lost during tx */
#define SCC_UART_TX_BD_NS	0x0080		/* no stop bit transmitted */
#define SCC_UART_TX_BD_PREAMBLE	0x0100		/* enable preamble */
#define SCC_UART_TX_BD_CM	0x0200		/* continous mode */
#define SCC_UART_TX_BD_ADDR	0x0400		/* buffer contains address */
#define SCC_UART_TX_BD_CTSR	0x0800		/* normal cts error reporting */
#define SCC_UART_TX_BD_INT	0x1000		/* interrupt generated */
#define SCC_UART_TX_BD_WRAP	0x2000		/* wrap back to first BD */
#define SCC_UART_TX_BD_READY	0x8000		/* buffer is being sent */

/* SCC Buffer */

typedef struct          /* SCC_BUF */
    {
    volatile UINT16	statusMode;	/* status and control */
    UINT16		dataLength;	/* length of data buffer in bytes */
    u_char *		dataPointer;	/* points to data buffer */
    } SCC_BUF;

/* SCC Parameters */

typedef struct          /* SCC_PARAM */
    {		                /* offset description*/
    volatile INT16      rbase;	/* 00 Rx buffer descriptor base address */
    volatile INT16      tbase;	/* 02 Tx buffer descriptor base address */
    volatile INT8       rfcr;	/* 04 Rx function code */
    volatile INT8       tfcr;	/* 05 Tx function code */
    volatile INT16      mrblr;	/* 06 maximum receive buffer length */
    volatile INT32      rstate;	/* 08 Rx internal state */
    volatile INT32      res1;	/* 0C Rx internal data pointer */
    volatile INT16      rbptr;	/* 10 Rx buffer descriptor pointer */
    volatile INT16      res2;	/* 12 reserved/internal */
    volatile INT32      res3;	/* 14 reserved/internal */
    volatile INT32      tstate;	/* 18 Tx internal state */
    volatile INT32      res4;	/* 1C reserved/internal */
    volatile INT16      tbptr;	/* 20 Tx buffer descriptor pointer */
    volatile INT16      res5;	/* 22 reserved/internal */
    volatile INT32      res6;	/* 24 reserved/internal */
    volatile INT32	rcrc;	/* 28 temp receive CRC */
    volatile INT32	tcrc;	/* 2C temp transmit CRC */
    } SCC_PARAM;
   
typedef struct          /* SCC */
    {
    SCC_PARAM   param;                  /* SCC parameters */
    char        prot[64];               /* protocol specific area */
    } SCC;

typedef struct          /* SCC_REG */
    {
    UINT32      	gsmrl;		/* SCC general mode register - low */
    UINT32      	gsmrh;  	/* SCC eneral mode register - high */
    UINT16      	psmr;   	/* SCC protocol mode register */
    UINT16      	res1;   	/* reserved */
    UINT16      	todr;   	/* SCC transmit on demand */
    UINT16      	dsr;    	/* SCC data sync. register */
    volatile UINT16     scce;   	/* SCC event register */
    UINT16      	res2;   	/* reserved */
    UINT16      	sccm;   	/* SCC mask register */
    UINT8       	res3;   	/* reserved */
    volatile UINT8      sccs;   	/* SCC status register */
    } SCC_REG;

/* PIP related definitions: */

#define CPM_PIP_STB         0x00010000	/* printer data-strobe control */
#define CPM_PIP_ACK         0x00020000	/* printer acknowledge status */
#define CPM_PIP_BSY         0x00000001	/* printer busy status */
#define CPM_PIP_SEL         0x00000002	/* printer select status */
#define CPM_PIP_PE          0x00000004	/* printer paper error status */
#define CPM_PIP_F           0x00000008	/* printer error/fault status */
#define CPM_PIP_DATA        0x0000ff00	/* data mask */

/* I2C related definitions */

/* I2C receive buffer descriptor control/status */

#define CPM_I2C_R_CS_E     0x8000   /* empty */
#define CPM_I2C_R_CS_W     0x2000   /* wrap, final BD in table */
#define CPM_I2C_R_CS_I     0x1000   /* interrupt */
#define CPM_I2C_R_CS_L     0x0800   /* buffer closed on start/stop/error */
#define CPM_I2C_R_CS_OV    0x0002   /* overrun */

/* I2C mode register bit definitions */

#define CPM_I2C_MODE_REVD            0x0020  /* reverse data */
#define CPM_I2C_MODE_GCD             0x0010  /* general call disable */
#define CPM_I2C_MODE_FLT             0x0008  /* clock filter */
#define CPM_I2C_MODE_PDIV_MASK       0x0006  /* predivider mask */
#define CPM_I2C_MODE_PDIV_BRGCLK32   0x0000  /* predivider - BRGCLK/32 */
#define CPM_I2C_MODE_PDIV_BRGCLK16   0x0002  /* predivider - BRGCLK/16 */
#define CPM_I2C_MODE_PDIV_BRGCLK8    0x0004  /* predivider - BRGCLK/8 */
#define CPM_I2C_MODE_PDIV_BRGCLK4    0x0006  /* predivider - BRGCLK/4 */
#define CPM_I2C_MODE_EN              0x0001  /* enable i2c */

/* I2C event/mask register bit definitions */

#define CPM_I2C_ER_TXE        0x0010  /* transmit error */
#define CPM_I2C_ER_BSY        0x0004  /* busy condition */
#define CPM_I2C_ER_TXB        0x0002  /* transmit buffer */
#define CPM_I2C_ER_RXB        0x0001  /* receive buffer */

/* I2C command register bit definitions */

#define CPM_I2C_COMMAND_STR  0x0080  /* start transmit */
#define CPM_I2C_COMMAND_MS   0x0001  /* master/slave mode */

/* I2C transmit buffer descriptor control/status */

#define CPM_I2C_T_CS_R       0x8000  /* ready */
#define CPM_I2C_T_CS_W       0x2000  /* wrap, final BD in table */
#define CPM_I2C_T_CS_I       0x1000  /* interrupt */
#define CPM_I2C_T_CS_L       0x0800  /* last buffer of message */
#define CPM_I2C_T_CS_S       0x0400  /* transmit start condition */
#define CPM_I2C_T_CS_NAK     0x0004  /* no acknowledge */
#define CPM_I2C_T_CS_UN      0x0002  /* underrun */
#define CPM_I2C_T_CS_CL      0x0001  /* collision */

#ifdef __cplusplus
}
#endif

#endif /* __INCppc860Cpmh */