ppc860cpm.h

PowerPC与PC微机串行通信

#define SPMODE_REV		0x0400	/* Reverse Data */
#define SPMODE_MS		0x0200	/* SPI Master */
#define SPMODE_EN		0x0100	/* Enable SPI */
#define SPMODE_LEN_MSK		0x00f0	/* Character Length */
#define SPMODE_LEN_1_BIT	0x0000	/* Character Length: 1 bit */
#define SPMODE_LEN_2_BITS	0x0010	/* Character Length: 2 bits */
#define SPMODE_LEN_3_BITS	0x0020	/* Character Length: 3 bits */
#define SPMODE_LEN_4_BITS	0x0030	/* Character Length: 4 bits */
#define SPMODE_LEN_5_BITS	0x0040	/* Character Length: 5 bits */
#define SPMODE_LEN_6_BITS	0x0050	/* Character Length: 6 bits */
#define SPMODE_LEN_7_BITS	0x0060	/* Character Length: 7 bits */
#define SPMODE_LEN_8_BITS	0x0070	/* Character Length: 8 bits */
#define SPMODE_LEN_9_BITS	0x0080	/* Character Length: 9 bits */
#define SPMODE_LEN_10_BITS	0x0090	/* Character Length: 10 bits */
#define SPMODE_LEN_11_BITS	0x00a0	/* Character Length: 11 bits */
#define SPMODE_LEN_12_BITS	0x00b0	/* Character Length: 12 bits */
#define SPMODE_LEN_13_BITS	0x00c0	/* Character Length: 13 bits */
#define SPMODE_LEN_14_BITS	0x00d0	/* Character Length: 14 bits */
#define SPMODE_LEN_15_BITS	0x00e0	/* Character Length: 15 bits */
#define SPMODE_LEN_16_BITS	0x00f0	/* Character Length: 16 bits */
#define SPMODE_PM_MSK		0x000f	/* BRGCLK Prescale Modulus select mask*/
#define SPMODE_PM_DIV4		0x0000	/* BRGCLK clock divided by 4 */
#define SPMODE_PM_DIV8		0x0001	/* BRGCLK clock divided by 8 */
#define SPMODE_PM_DIV12		0x0002	/* BRGCLK clock divided by 12 */
#define SPMODE_PM_DIV16		0x0003	/* BRGCLK clock divided by 16 */
#define SPMODE_PM_DIV20		0x0004	/* BRGCLK clock divided by 20 */
#define SPMODE_PM_DIV24		0x0005	/* BRGCLK clock divided by 24 */
#define SPMODE_PM_DIV28		0x0006	/* BRGCLK clock divided by 28 */
#define SPMODE_PM_DIV32		0x0007	/* BRGCLK clock divided by 32 */
#define SPMODE_PM_DIV36		0x0008	/* BRGCLK clock divided by 36 */
#define SPMODE_PM_DIV40		0x0009	/* BRGCLK clock divided by 40 */
#define SPMODE_PM_DIV44		0x000a	/* BRGCLK clock divided by 44 */
#define SPMODE_PM_DIV48		0x000b	/* BRGCLK clock divided by 48 */
#define SPMODE_PM_DIV52		0x000c	/* BRGCLK clock divided by 52 */
#define SPMODE_PM_DIV56		0x000d	/* BRGCLK clock divided by 56 */
#define SPMODE_PM_DIV60		0x000e	/* BRGCLK clock divided by 60 */
#define SPMODE_PM_DIV64		0x000f	/* BRGCLK clock divided by 64 */

/* SPI Command Register (SPCOM - 0x0AAD) */

#define SPCOM_STR		0x80	/* Start Transmit */


/* SCC Receive Function Code Register bit definition (RFCR) */

#define RFCR_BO_MSK		0x18	/* Byte Order Mask */
#define RFCR_BO_DEC_LE		0x00	/* Byte Order: DEC little endian mode */
#define RFCR_BO_PPC_LE		0x08	/* Byte Order: PPC little endian mode */
					/* reverse transmission order of */
					/* bytes compared to DEC/Intel mode */
#define RFCR_BO_MOT_BE		0x18	/* Motorola Big endian mode */
#define RFCR_AT_MSK		0x07	/* Address Type Mask */

/* SCC Transmit Function Code Register bit definition (TFCR) */ 

#define TFCR_BO_MSK		0x18	/* Byte Order Mask */
#define TFCR_BO_DEC_LE		0x00	/* Byte Order: DEC little endian mode */
#define TFCR_BO_PPC_LE		0x08	/* Byte Order: PPC little endian mode */
					/* reverse transmission order of */
					/* bytes compared to DEC/Intel mode */
#define TFCR_BO_MOT_BE		0x18	/* Motorola Big endian mode */
#define TFCR_AT_MSK		0x07	/* Address Type Mask */

/* SMC UART Mode Register bit definition (SMCMR - 0x0A82) */

#define	SMCMR_CLEN_MSK		0x7800	/* Character Length Mask */
#define SMCMR_CLEN_0_BIT	0x0000	/* Character Length: 0 bit */
#define SMCMR_CLEN_1_BIT	0x0800	/* Character Length: 1 bit */
#define SMCMR_CLEN_2_BITS	0x1000	/* Character Length: 2 bits */
#define SMCMR_CLEN_3_BITS	0x1800	/* Character Length: 3 bits */
#define SMCMR_CLEN_4_BITS	0x2000	/* Character Length: 4 bits */
#define SMCMR_CLEN_5_BITS	0x2800	/* Character Length: 5 bits */
#define SMCMR_CLEN_6_BITS	0x3000	/* Character Length: 6 bits */
#define SMCMR_CLEN_7_BITS	0x3800	/* Character Length: 7 bits */
#define SMCMR_CLEN_8_BITS	0x4000	/* Character Length: 8 bits */
#define SMCMR_CLEN_9_BITS	0x4800	/* Character Length: 9 bits */
#define SMCMR_CLEN_10_BITS	0x5000	/* Character Length: 10 bits */
#define SMCMR_CLEN_11_BITS	0x5800	/* Character Length: 11 bits */
#define SMCMR_CLEN_12_BITS	0x6000	/* Character Length: 12 bits */
#define SMCMR_CLEN_13_BITS	0x6800	/* Character Length: 13 bits */
#define SMCMR_CLEN_14_BITS	0x7000	/* Character Length: 14 bits */
#define SMCMR_CLEN_15_BITS	0x7800	/* Character Length: 15 bits */
#define SMCMR_SL		0x0400	/* Stop Length */		
#define SMCMR_SL_1_BIT		0x0000	/* Stop Length: 1 bit */		
#define SMCMR_SL_2_BITS		0x0400	/* Stop Length: 2 bits */		
#define SMCMR_PEN		0x0200	/* Parity Enable */
#define SMCMR_PM		0x0100	/* Parity Mode */
#define SMCMR_PM_ODD		0x0000	/* Parity Mode: Odd parity */
#define SMCMR_PM_EVEN		0x0100	/* Parity Mode: Even parity */
#define SMCMR_SM_MSK		0x0030	/* SMC Mode Mask */
#define SMCMR_SM_GCI_SCIT	0x0000	/* SMC Mode: GCI or SCIT support */
#define SMCMR_SM_UART		0x0020	/* SMC Mode: GCI or SCIT support */
#define SMCMR_SM_TRANSPARENT	0x0030	/* SMC Mode: Totally transparent */
#define SMCMR_DM_MSK		0x000c	/* Diagnostic Mode Mask */
#define SMCMR_DM_NORMAL		0x0000	/* Diagnostic Mode: Normal */
#define SMCMR_DM_LCLB		0x0004	/* Diagnostic Mode: Local Loopback */
#define SMCMR_DM_ECHO		0x0008	/* Diagnostic Mode: Echo */
#define SMCMR_TEN		0x0002	/* SMC Transmit Enable */
#define SMCMR_REN		0x0001	/* SMC Receive Enable */

#define SMCMR_STD_MODE  	(SMCMR_CLEN_9_BITS | \
				 SMCMR_SL_1_BIT    | \
				 SMCMR_SM_UART	   | \
				 SMCMR_DM_NORMAL)


#define SCMCR_STD_MODE_ENABLED	(SMCMR_STD_MODE	| \
				 SMCMR_TEN	| \
				 SMCMR_REN)

/* CPM Interrupt Vector Register (CIVR - 0x930) */

#define CIVR_IVN_MSK		0xf800		/* Interrupt Vector Number */
#define CIVR_IACK		0x0001		/* Interrupt Acknowledge */

/* CPM Interrupt configuration Register (CICR - 0x940) */

#define CICR_SCCDP_MSK		0xc00000	/* SCCd Priority Order Mask */
#define CICR_SCCDP_SCC1		0x000000	/* SCC1 asserts the SCCd */ 
#define CICR_SCCDP_SCC2		0x400000	/* SCC2 asserts the SCCd */ 
#define CICR_SCCDP_SCC3		0x800000	/* SCC3 asserts the SCCd */ 
#define CICR_SCCDP_SCC4		0xc00000	/* SCC4 asserts the SCCd */ 
#define CICR_SCCCP_MSK		0x300000	/* SCCc Priority Order Mask */
#define CICR_SCCCP_SCC1		0x000000	/* SCC1 asserts the SCCc */ 
#define CICR_SCCCP_SCC2		0x100000	/* SCC2 asserts the SCCc */ 
#define CICR_SCCCP_SCC3		0x200000	/* SCC3 asserts the SCCc */ 
#define CICR_SCCCP_SCC4		0x300000	/* SCC4 asserts the SCCc */ 
#define CICR_SCCBP_MSK		0x0c0000	/* SCCb Priority Order Mask */
#define CICR_SCCBP_SCC1		0x000000	/* SCC1 asserts the SCCb */ 
#define CICR_SCCBP_SCC2		0x040000	/* SCC2 asserts the SCCb */ 
#define CICR_SCCBP_SCC3		0x080000	/* SCC3 asserts the SCCb */ 
#define CICR_SCCBP_SCC4		0x0c0000	/* SCC4 asserts the SCCb */ 
#define CICR_SCCAP_MSK		0x030000	/* SCCa Priority Order Mask */
#define CICR_SCCAP_SCC1		0x000000	/* SCC1 asserts the SCCa */ 
#define CICR_SCCAP_SCC2		0x010000	/* SCC2 asserts the SCCa */ 
#define CICR_SCCAP_SCC3		0x020000	/* SCC3 asserts the SCCa */ 
#define CICR_SCCAP_SCC4		0x030000	/* SCC4 asserts the SCCa */ 
#define CICR_IRL_MSK		0x00e000	/* Interrupt Request Level */
#define CICR_IRL_LVL0		0x000000	/* Interrupt Request Level 0 */
#define CICR_IRL_LVL1		0x002000	/* Interrupt Request Level 1 */
#define CICR_IRL_LVL2		0x004000	/* Interrupt Request Level 2 */
#define CICR_IRL_LVL3		0x006000	/* Interrupt Request Level 3 */
#define CICR_IRL_LVL4		0x008000	/* Interrupt Request Level 4 */
#define CICR_IRL_LVL5		0x00a000	/* Interrupt Request Level 5 */
#define CICR_IRL_LVL6		0x00c000	/* Interrupt Request Level 6 */
#define CICR_IRL_LVL7		0x00e000	/* Interrupt Request Level 7 */
#define CICR_HP_MSK		0x001f00	/* Highest Priority */
#define CICR_IEN		0x000080	/* Interrupt Enable */
#define CICR_SPS		0x000001	/* Spread Priority Scheme */

/* CPM Interrupt Pending Register (CIPR - 0x944) */

#define CIPR_PC15		0x80000000	/* Parallel I/O Port C[15] */
#define CIPR_SCC1		0x40000000	/* SCC 1 */
#define CIPR_SCC2		0x20000000	/* SCC 2 */
#define CIPR_SCC3		0x10000000	/* SCC 3 */
#define CIPR_SCC4		0x08000000	/* SCC 4 */
#define CIPR_PC14		0x04000000	/* Parallel I/O Port C[14] */
#define CIPR_TIMER1		0x02000000	/* Timer 1 */
#define CIPR_PC13		0x01000000	/* Parallel I/O Port C[13] */
#define CIPR_PC12		0x00800000	/* Parallel I/O Port C[12] */
#define CIPR_SDMA		0x00400000	/* SDMA bus error */
#define CIPR_IDMA1		0x00200000	/* IDMA 1 */	
#define CIPR_IDMA2		0x00100000	/* IDMA 2 */	
#define CIPR_TIMER2		0x00040000	/* Timer 2 */
#define CIPR_R_TT		0x00020000	/* Risc Timer Table */
#define CIPR_I2C		0x00010000	/* I2C */
#define CIPR_PC11		0x00008000	/* Parallel I/O Port C[11] */
#define CIPR_PC10		0x00004000	/* Parallel I/O Port C[10] */
#define CIPR_TIMER3		0x00001000	/* Timer 3 */
#define CIPR_PC9		0x00000800	/* Parallel I/O Port C[9] */
#define CIPR_PC8		0x00000400	/* Parallel I/O Port C[8] */
#define CIPR_PC7		0x00000200	/* Parallel I/O Port C[7] */
#define CIPR_TIMER4		0x00000080	/* Timer 4 */
#define CIPR_PC6		0x00000040	/* Parallel I/O Port C[6] */
#define CIPR_SPI		0x00000020	/* SPI */
#define CIPR_SMC1		0x00000010	/* SMC 1 */
#define CIPR_SMC2_PIP		0x00000008	/* SMC 1 */
#define CIPR_PC5		0x00000004	/* Parallel I/O Port C[5] */
#define CIPR_PC4		0x00000002	/* Parallel I/O Port C[4] */

/* CPM Interrupt Mask Register (CIMR - 0x948) */

#define CIMR_PC15		0x80000000	/* Parallel I/O Port C[15] */
#define CIMR_SCC1		0x40000000	/* SCC 1 */
#define CIMR_SCC2		0x20000000	/* SCC 2 */
#define CIMR_SCC3		0x10000000	/* SCC 3 */
#define CIMR_SCC4		0x08000000	/* SCC 4 */
#define CIMR_PC14		0x04000000	/* Parallel I/O Port C[14] */
#define CIMR_TIMER1		0x02000000	/* Timer 1 */
#define CIMR_PC13		0x01000000	/* Parallel I/O Port C[13] */
#define CIMR_PC12		0x00800000	/* Parallel I/O Port C[12] */
#define CIMR_SDMA		0x00400000	/* SDMA bus error */
#define CIMR_IDMA1		0x00200000	/* IDMA 1 */	
#define CIMR_IDMA2		0x00100000	/* IDMA 2 */	
#define CIMR_TIMER2		0x00040000	/* Timer 2 */
#define CIMR_R_TT		0x00020000	/* Risc Timer Table */
#define CIMR_I2C		0x00010000	/* I2C */
#define CIMR_PC11		0x00008000	/* Parallel I/O Port C[11] */
#define CIMR_PC10		0x00004000	/* Parallel I/O Port C[10] */
#define CIMR_TIMER3		0x00001000	/* Timer 3 */
#define CIMR_PC9		0x00000800	/* Parallel I/O Port C[9] */
#define CIMR_PC8		0x00000400	/* Parallel I/O Port C[8] */
#define CIMR_PC7		0x00000200	/* Parallel I/O Port C[7] */
#define CIMR_TIMER4		0x00000080	/* Timer 4 */
#define CIMR_PC6		0x00000040	/* Parallel I/O Port C[6] */
#define CIMR_SPI		0x00000020	/* SPI */
#define CIMR_SMC1		0x00000010	/* SMC 1 */
#define CIMR_SMC2_PIP		0x00000008	/* SMC 1 */
#define CIMR_PC5		0x00000004	/* Parallel I/O Port C[5] */
#define CIMR_PC4		0x00000002	/* Parallel I/O Port C[4] */
#define CIMR_ALL		0xfff7defe	/* all interrupt masks */

/* CPM Interrupt in Service Register (CISR - 0x94c) */

#define CISR_PC15		0x80000000	/* Parallel I/O Port C[15] */
#define CISR_SCC1		0x40000000	/* SCC 1 */
#define CISR_SCC2		0x20000000	/* SCC 2 */
#define CISR_SCC3		0x10000000	/* SCC 3 */
#define CISR_SCC4		0x08000000	/* SCC 4 */
#define CISR_PC14		0x04000000	/* Parallel I/O Port C[14] */
#define CISR_TIMER1		0x02000000	/* Timer 1 */
#define CISR_PC13		0x01000000	/* Parallel I/O Port C[13] */
#define CISR_PC12		0x00800000	/* Parallel I/O Port C[12] */
#define CISR_SDMA		0x00400000	/* SDMA bus error */
#define CISR_IDMA1		0x00200000	/* IDMA 1 */	
#define CISR_IDMA2		0x00100000	/* IDMA 2 */	
#define CISR_TIMER2		0x00040000	/* Timer 2 */
#define CISR_R_TT		0x00020000	/* Risc Timer Table */
#define CISR_I2C		0x00010000	/* I2C */
#define CISR_PC11		0x00008000	/* Parallel I/O Port C[11] */
#define CISR_PC10		0x00004000	/* Parallel I/O Port C[10] */
#define CISR_TIMER3		0x00001000	/* Timer 3 */
#define CISR_PC9		0x00000800	/* Parallel I/O Port C[9] */
#define CISR_PC8		0x00000400	/* Parallel I/O Port C[8] */
#define CISR_PC7		0x00000200	/* Parallel I/O Port C[7] */
#define CISR_TIMER4		0x00000080	/* Timer 4 */
#define CISR_PC6		0x00000040	/* Parallel I/O Port C[6] */
#define CISR_SPI		0x00000020	/* SPI */
#define CISR_SMC1		0x00000010	/* SMC 1 */
#define CISR_SMC2_PIP		0x00000008	/* SMC 1 */
#define CISR_PC5		0x00000004	/* Parallel I/O Port C[5] */
#define CISR_PC4		0x00000002	/* Parallel I/O Port C[4] */

/* SCC - Serial Communication Controller */


/* General SCC Mode Register definitions  */

#define SCC_GSMRL_HDLC		0x00000000	/* HDLC mode */
#define SCC_GSMRL_APPLETALK	0x00000002	/* AppleTalk mode (LocalTalk) */
#define SCC_GSMRL_SS7		0x00000003	/* SS7 mode (microcode) */
#define SCC_GSMRL_UART		0x00000004	/* UART mode */
#define SCC_GSMRL_PROFI_BUS	0x00000005	/* Profi-Bus mode (microcode) */
#define SCC_GSMRL_ASYNC_HDLC	0x00000006	/* async HDLC mode (microcode)*/
#define SCC_GSMRL_V14		0x00000007	/* V.14 mode */
#define SCC_GSMRL_BISYNC	0x00000008	/* BISYNC mode */
#define SCC_GSMRL_DDCMP		0x00000009	/* DDCMP mode (microcode) */
#define SCC_GSMRL_ETHERNET	0x0000000c	/* ethernet mode (SCC1 only) */
#define SCC_GSMRL_ENT		0x00000010	/* enable transmitter */