ppc860cpm.h

PowerPC与PC微机串行通信

#define CPM_CR_SPI_CLOSE        CPM_CR_OPCODE_CLOSE	/* close rx buffer */

#define CPM_CR_I2C_INIT_RT      CPM_CR_OPCODE_INIT_RT	/* rx and tx init */
#define CPM_CR_I2C_INIT_R       CPM_CR_OPCODE_INIT_R	/* init rx only */
#define CPM_CR_I2C_INIT_T       CPM_CR_OPCODE_INIT_T	/* init tx only */
#define CPM_CR_I2C_CLOSE        CPM_CR_OPCODE_CLOSE	/* close rx buffer */

#define CPM_CR_IDMA_INIT	CPM_CR_OPCODE_IDMA_INIT	/* IDMA init */
#define CPM_CR_IDMA_STOP	CPM_CR_OPCODE_IDMA_STOP	/* IDMA stop */

#define CPM_CR_DSP_START	CPM_CR_OPCODE_DSP_START	/* DSP start */
#define CPM_CR_DSP_INIT		CPM_CR_OPCODE_DSP_INIT	/* DSP init */

#define CPM_CR_TIMER_SET	CPM_CR_OPCODE_SET_ITMR	/* TIMER set */

/* UART Even Register bit definition (SCCE - 0x0A10) */

#define SCCE_GLR		0x1000	/* Glitch on Receiver */
#define SCCE_GLT		0x0800	/* Glitch on Transmitter */
#define SCCE_AB			0x0200	/* Auto Baud */
#define SCCE_IDL		0x0100	/* Idle Sequence Status Changed */
#define SCCE_GRA		0x0080	/* Graceful stop complete */
#define SCCE_BRKE		0x0040	/* Break End */
#define SCCE_BRKS		0x0020	/* Break Start */
#define SCCE_CCR		0x0008	/* Control Character Received */
#define SCCE_BSY		0x0004	/* Busy Condition */
#define SCCE_TX			0x0002	/* Transmitter Buffer */
#define SCCE_RX			0x0001	/* Receiver Buffer */

/* SCC Status Register bit definition (SCCS - 0x0A17) */

#define SCCS_ID			0x01	/* Idle Status */

/* SI Mode Register bit definition (SIMODE - 0xAE0) */

#define SIMODE_SMC2_MUX		0x80000000	/* connected to mux SI */
#define SIMODE_SMC2_NMSI	0x00000000	/* NMSI mode */
#define SIMODE_SMC2CS_BRG1	0x00000000	/* BRG1 is clock source */
#define SIMODE_SMC2CS_BRG2	0x10000000	/* BRG2 is clock source */
#define SIMODE_SMC2CS_BRG3	0x20000000	/* BRG3 is clock source */
#define SIMODE_SMC2CS_BRG4	0x30000000	/* BRG4 is clock source */
#define SIMODE_SMC2CS_CLK5	0x40000000	/* CLK5 is clock source */
#define SIMODE_SMC2CS_CLK6	0x50000000	/* CLK6 is clock source */
#define SIMODE_SMC2CS_CLK7	0x60000000	/* CLK7 is clock source */
#define SIMODE_SMC2CS_CLK8	0x70000000	/* CLK8 is clock source */
#define SIMODE_SDMB_MSK		0x0c000000	/* SI Diagnostic Mode - TDM B */
#define SIMODE_SDMB_NORM	0x00000000	/* Diag Mode-normal operation */
#define SIMODE_SDMB_ECHO	0x04000000	/* Diag Mode-auto echo */
#define SIMODE_SDMB_LOOP	0x08000000	/* Diag Mode-internal loopback*/
#define SIMODE_SDMB_LCTR	0x0C000000	/* Diag Mode-loopback control */
#define SIMODE_RFSDB_MSK	0x03000000	/* Receive Frame Delay TDM B */
#define SIMODE_RFSDB_NO_DELAY	0x00000000	/* Receive Delay - No Delay */
#define SIMODE_RFSDB_1BIT	0x01000000	/* Receive Delay - 1bit delay */
#define SIMODE_RFSDB_2BIT	0x02000000	/* Receive Delay - 2bit delay */
#define SIMODE_RFSDB_3BIT	0x03000000	/* Receive Delay - 3bit delay */
#define SIMODE_DSCB		0x00800000	/* Double Speed Clocl TDM B */
#define SIMODE_CRTB		0x00400000	/* Common Rcv and Trans. pins */
#define SIMODE_STZB		0x00200000	/* Set L1TxDx to Zero TDM B */
#define SIMODE_CEB_FALLING	0x00000000	/* Clock Edge - falling */
#define SIMODE_CEB_RISING	0x00100000	/* Clock Edge - rising */
#define SIMODE_FEB_FALLING	0x00000000	/* Frame Sync Edge - falling  */
#define SIMODE_FEB_RISING	0x00080000	/* Frame Sync Edge - rising */
#define SIMODE_GMB_GCI_SCIT	0x00000000	/* Grant Mode - GCI/SCIT */
#define SIMODE_GMB_IDL		0x00040000	/* Grant Mode - idle */
#define SIMODE_TFSDB_MSK	0x00030000	/* Transmit Frame Sync Delay */
#define SIMODE_TFSDB_NO_DELAY	0x00000000	/* Transmit Delay - No Delay */
#define SIMODE_TFSDB_1BIT	0x00010000	/* Transmit Delay - 1bit */
#define SIMODE_TFSDB_2BIT	0x00020000	/* Transmit Delay - 2bit */
#define SIMODE_TFSDB_3BIT	0x00030000	/* Transmit Delay - 3bit */


#define SIMODE_SMC1_MUX		0x00008000	/* connected to mux SI */
#define SIMODE_SMC1_NMSI	0x00000000	/* NMSI mode */
#define SIMODE_SMC1CS_BRG1	0x00000000	/* BRG1 is clock source */
#define SIMODE_SMC1CS_BRG2	0x00001000	/* BRG2 is clock source */
#define SIMODE_SMC1CS_BRG3	0x00002000	/* BRG3 is clock source */
#define SIMODE_SMC1CS_BRG4	0x00003000	/* BRG4 is clock source */
#define SIMODE_SMC1CS_CLK1	0x00004000	/* CLK1 is clock source */
#define SIMODE_SMC1CS_CLK2	0x00005000	/* CLK2 is clock source */
#define SIMODE_SMC1CS_CLK3	0x00006000	/* CLK3 is clock source */
#define SIMODE_SMC1CS_CLK4	0x00007000	/* CLK4 is clock source */
#define SIMODE_SDMA_MSK		0x00000c00	/* SI Diagnostic Mode - TDM B */
#define SIMODE_SDMA_NORM	0x00000000	/* Diag Mode-normal operation */
#define SIMODE_SDMA_ECHO	0x00000400	/* Diag Mode-auto echo */
#define SIMODE_SDMA_LOOP	0x00000800	/* Diag Mode-internal loopback*/
#define SIMODE_SDMA_LCTR	0x00000C00	/* Diag Mode-loopback control */
#define SIMODE_RFSDA_MSK	0x00000300	/* Receive Frame Delay TDM A */
#define SIMODE_RFSDA_NO_DELAY	0x00000000	/* Receive Delay - No Delay */
#define SIMODE_RFSDA_1BIT_DELAY	0x00000100	/* Receive Delay - 1bit delay */
#define SIMODE_RFSDA_2BIT_DELAY	0x00000200	/* Receive Delay - 2bit delay */
#define SIMODE_RFSDA_3BIT_DELAY	0x00000300	/* Receive Delay - 3bit delay */
#define SIMODE_DSCA		0x00000080	/* Double Speed Clocl TDM A */
#define SIMODE_CRTA		0x00000040	/* Common Rcv and Trans. pins */
#define SIMODE_STZA		0x00000020	/* Set L1TxDx to Zero TDM A */
#define SIMODE_CEA_FALLING	0x00000000	/* Clock Edge - falling */
#define SIMODE_CEA_RISING	0x00000010	/* Clock Edge - rising */
#define SIMODE_FEA_FALLING	0x00000000	/* Frame Sync Edge - falling  */
#define SIMODE_FEA_RISING	0x00000008	/* Frame Sync Edge - rising */
#define SIMODE_GMA_GCI_SCIT	0x00000000	/* Grant Mode - GCI/SCIT */
#define SIMODE_GMA_IDL		0x00000004	/* Grant Mode - idle */
#define SIMODE_TFSDA_MSK	0x00000003	/* Transmit Frame Sync Delay */
#define SIMODE_TFSDA_NO_DELAY	0x00000000	/* Transmit Delay - No Delay */
#define SIMODE_TFSDA_1BIT	0x00000001	/* Transmit Delay - 1bit */
#define SIMODE_TFSDA_2BIT	0x00000002	/* Transmit Delay - 2bit */
#define SIMODE_TFSDA_3BIT	0x00000003	/* Transmit Delay - 3bit */

/* SI Global Mode Register bit definition (SIGMR - 0xAE4) */

#define SIGMR_ENB	0x08		/* Enable Channel B */
#define SIGMR_ENA	0x04		/* Enable Channel A */
#define SIGMR_RDM_MSK	0x03		/* Ram Division Mode mask */

/* SI Status Register bit definition (SISTR - 0xAE6) */

#define SISTR_CRORA		0x80	/* Current Route of TDM A Receiver */
#define SISTR_CROTA		0x40	/* Current Route of TDM A Transmitter */
#define SISTR_CRORB		0x20	/* Current Route of TDM B Receiver */
#define SISTR_CROTB		0x10	/* Current Route of TDM B Transmitter */

/* SI Command Register bit definition (SICMR - 0xAE7) */

#define SICMR_CSRRA		0x80	/* Change Shadow RAM - TDM A Receiver */
#define SICMR_CSRTA		0x40	/* Change Shadow RAM - TDM A Transmit */
#define SICMR_CSRRB		0x20	/* Change Shadow RAM - TDM B Receiver */
#define SICMR_CSRTB		0x10	/* Change Shadow RAM - TDM B Transmit */

/* SI Clock Route Register bit definition (SICR - 0xAEC) */

#define SICR_GR4		0x80000000	/* Grant Support of SCC4 */
#define SICR_SC4_MUX		0x40000000	/* SCC4 Connection - mux SI */
#define SICR_R4CS_MSK		0x38000000	/* SCC4 Receive Clock Source */
#define SICR_R4CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_R4CS_BRG2		0x08000000	/* BRG2 clock source */
#define SICR_R4CS_BRG3		0x10000000	/* BRG3 clock source */
#define SICR_R4CS_BRG4		0x18000000	/* BRG4 clock source */
#define SICR_R4CS_CLK5		0x20000000	/* CLK5 clock source */
#define SICR_R4CS_CLK6		0x28000000	/* CLK6 clock source */
#define SICR_R4CS_CLK7		0x30000000	/* CLK7 clock source */
#define SICR_R4CS_CLK8		0x38000000	/* CLK8 clock source */
#define SICR_T4CS_MSK		0x07000000	/* SCC4 Transmit Clock Source */
#define SICR_T4CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_T4CS_BRG2		0x01000000	/* BRG2 clock source */
#define SICR_T4CS_BRG3		0x02000000	/* BRG3 clock source */
#define SICR_T4CS_BRG4		0x03000000	/* BRG4 clock source */
#define SICR_T4CS_CLK5		0x04000000	/* CLK5 clock source */
#define SICR_T4CS_CLK6		0x05000000	/* CLK6 clock source */
#define SICR_T4CS_CLK7		0x06000000	/* CLK7 clock source */
#define SICR_T4CS_CLK8		0x07000000	/* CLK8 clock source */

#define SICR_GR3		0x00800000	/* Grant Support of SCC3 */
#define SICR_SC3_MUX		0x00400000	/* SCC3 Connection - mux SI */
#define SICR_R3CS_MSK		0x00380000	/* SCC3 Receive Clock Source */
#define SICR_R3CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_R3CS_BRG2		0x00080000	/* BRG2 clock source */
#define SICR_R3CS_BRG3		0x00100000	/* BRG3 clock source */
#define SICR_R3CS_BRG4		0x00180000	/* BRG4 clock source */
#define SICR_R3CS_CLK5		0x00200000	/* CLK5 clock source */
#define SICR_R3CS_CLK6		0x00280000	/* CLK6 clock source */
#define SICR_R3CS_CLK7		0x00300000	/* CLK7 clock source */
#define SICR_R3CS_CLK8		0x00380000	/* CLK8 clock source */
#define SICR_T3CS_MSK		0x00070000	/* SCC3 Transmit Clock Source */
#define SICR_T3CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_T3CS_BRG2		0x00010000	/* BRG2 clock source */
#define SICR_T3CS_BRG3		0x00020000	/* BRG3 clock source */
#define SICR_T3CS_BRG4		0x00030000	/* BRG4 clock source */
#define SICR_T3CS_CLK5		0x00040000	/* CLK5 clock source */
#define SICR_T3CS_CLK6		0x00050000	/* CLK6 clock source */
#define SICR_T3CS_CLK7		0x00060000	/* CLK7 clock source */
#define SICR_T3CS_CLK8		0x00070000	/* CLK8 clock source */

#define SICR_GR2		0x00008000	/* Grant Support of SCC2 */
#define SICR_SC2_MUX		0x00004000	/* SCC2 Connection - mux SI */
#define SICR_R2CS_MSK		0x00003800	/* SCC2 Receive Clock Source */
#define SICR_R2CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_R2CS_BRG2		0x00000800	/* BRG2 clock source */
#define SICR_R2CS_BRG3		0x00001000	/* BRG3 clock source */
#define SICR_R2CS_BRG4		0x00001800	/* BRG4 clock source */
#define SICR_R2CS_CLK1		0x00002000	/* CLK1 clock source */
#define SICR_R2CS_CLK2		0x00002800	/* CLK2 clock source */
#define SICR_R2CS_CLK3		0x00003000	/* CLK3 clock source */
#define SICR_R2CS_CLK4		0x00003800	/* CLK4 clock source */
#define SICR_T2CS_MSK		0x00000700	/* SCC2 Transmit Clock Source */
#define SICR_T2CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_T2CS_BRG2		0x00000100	/* BRG2 clock source */
#define SICR_T2CS_BRG3		0x00000200	/* BRG3 clock source */
#define SICR_T2CS_BRG4		0x00000300	/* BRG4 clock source */
#define SICR_T2CS_CLK1		0x00000400	/* CLK1 clock source */
#define SICR_T2CS_CLK2		0x00000500	/* CLK2 clock source */
#define SICR_T2CS_CLK3		0x00000600	/* CLK3 clock source */
#define SICR_T2CS_CLK4		0x00000700	/* CLK4 clock source */

#define SICR_GR1		0x00000080	/* Grant Support of SCC1 */
#define SICR_SC1_MUX		0x00000040	/* SCC1 Connection - mux SI */
#define SICR_R1CS_MSK		0x00000038	/* SCC1 Receive Clock Source */
#define SICR_R1CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_R1CS_BRG2		0x00000008	/* BRG2 clock source */
#define SICR_R1CS_BRG3		0x00000010	/* BRG3 clock source */
#define SICR_R1CS_BRG4		0x00000018	/* BRG4 clock source */
#define SICR_R1CS_CLK1		0x00000020	/* CLK1 clock source */
#define SICR_R1CS_CLK2		0x00000028	/* CLK2 clock source */
#define SICR_R1CS_CLK3		0x00000030	/* CLK3 clock source */
#define SICR_R1CS_CLK4		0x00000038	/* CLK4 clock source */
#define SICR_T1CS_MSK		0x00000007	/* SCC1 Transmit Clock Source */
#define SICR_T1CS_BRG1		0x00000000	/* BRG1 clock source */
#define SICR_T1CS_BRG2		0x00000001	/* BRG2 clock source */
#define SICR_T1CS_BRG3		0x00000002	/* BRG3 clock source */
#define SICR_T1CS_BRG4		0x00000003	/* BRG4 clock source */
#define SICR_T1CS_CLK1		0x00000004	/* CLK1 clock source */
#define SICR_T1CS_CLK2		0x00000005	/* CLK2 clock source */
#define SICR_T1CS_CLK3		0x00000006	/* CLK3 clock source */
#define SICR_T1CS_CLK4		0x00000007	/* CLK4 clock source */

/* SI Ram Pointer bit definition (SIRP - 0xAF0) */

#define SIRP_VTB_MSK		0x20000000	/* Transmitter B pointer Valid*/
#define SIRP_TBPTR_MSK		0x1f000000	/* Transmitter B pointer */
#define SIRP_VTA_MSK		0x00200000	/* Transmitter A pointer Valid*/
#define SIRP_TAPTR_MSK		0x001f0000	/* Transmitter A pointer */
#define SIRP_VRB_MSK		0x00002000	/* Receiver B pointer Valid */
#define SIRP_RBPTR_MSK		0x00001f00	/* Receiver B pointer */
#define SIRP_VRA_MSK		0x00000020	/* Receiver A pointer Valid */
#define SIRP_RAPTR_MSK		0x0000001f	/* Receiver A pointer */

/* SMC UART Event Register bit definition (SMCE - 0x0A86) */ 

#define SMCE_BRK		0x10	/* Break character received */
#define SMCE_BSY		0x04	/* Busy Condition */
#define SMCE_TX			0x02	/* Transmit Buffer */
#define SMCE_RX			0x01	/* Receive Buffer */
#define SMCE_ALL_EVENTS		(SMCE_BRK | SMCE_BSY | SMCE_TX | SMCE_RX)

/* SMC UART Mask Register bit definition (SMCM - 0x0A8A) */ 

#define SMCM_BRK_MSK		0x10	/* Break character received Mask */
#define SMCM_BSY_MSK		0x04	/* Busy Condition Mask */
#define SMCM_TX_MSK		0x02	/* Transmit Buffer Mask */
#define SMCM_RX_MSK		0x01	/* Receive Buffer Mask */

/* equates for CICR register CP interrupt configuration register */
#define CICR_IRL_LEVEL_0	0x00000000	/* highest interrupt level */
#define CICR_IRL_LEVEL_1	0x00020000
#define CICR_IRL_LEVEL_2	0x00040000
#define CICR_IRL_LEVEL_3	0x00060000
#define CICR_IRL_LEVEL_4	0x00080000	/* standard value */
#define CICR_IRL_LEVEL_5	0x000A0000
#define CICR_IRL_LEVEL_6	0x000C0000
#define CICR_IRL_LEVEL_7	0x000E0000	/* lowest */
#define CICR_HP_SRC_STD		0x0001F000	/* highest priority int */
#define CICR_MASTER_IEN		0x00000080	/* master interrupt enable */

/* SPI Mode Register bit definition (SPMODE - 0x0AA0) */

#define SPMODE_LOOP		0x4000	/* Loop Mode */
#define SPMODE_CI		0x2000	/* Clock Invert */
#define SPMODE_CI_LOW		0x0000	/* Inactive state is low */
#define SPMODE_CI_HIGH		0x2000	/* Inactive state is high */
#define SPMODE_CP		0x1000	/* Clock Phase */
#define SPMODE_CP_MIDDLE	0x0000	/* Clock Phase: middle of the data */
#define SPMODE_CP_BEGIN		0x1000	/* Clock Phase: Beginning of the data */
#define SPMODE_DIV16		0x0800	/* BRGCLK Divide by 16	*/