ppc860cpm.h

PowerPC与PC微机串行通信

/* ppc860Cpm.h - Motorola PPC860 Communication Processor Module header file */

/* Copyright 1984-1998 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,11jan99,cn   Corrected/added defines for CP commands (SPR# 20337),
		 added qualifier volatile where needed (SPR# 24295).
01f,09nov98,cn   Added support for Fast Ethernet Controller.
01e,20apr98,map  fixed SIMODE definitions [SPR# 20157]
01d,13apr98,map  added more SCC definitions.
01c,25mar98,map  added SCC, PIP, I2C, CPCR, definitions.
01b,09may96,dzb  added CPM_CR_... flags for the CPM command register.
01a,24apr96,tpr	 created.
*/

/*
 * This file contains constants of the Communication Processor Unit (SIU) for
 * the Motorola MPC860 PowerPC microcontroller.
 */

#ifndef __INCppc860Cpmh
#define __INCppc860Cpmh

#ifdef __cplusplus
extern "C" {
#endif

    
/* device and channel structures */

/* 
 * The PPC860SMC_CHAN structure defines a serial I/O channel which
 * describes the (TBD) registers for a given channel. 
 * Also the various SIO driver functions ( ioctl, txStarup, callbackInstall,
 * pollInput, polloutput ) that this channel could utilize are declared 
 * here.
 */

#ifdef	_ASMLANGUAGE
#  define SMC_ADRS(reg)	(MPC860SMC1_BASE + (reg * MPC860SMC1_REG_OFFSET))
#else
#  define SMC_ADRS(reg)	((VCHAR *)MPC860SMC1_BASE+(reg*MPC860SMC1_REG_OFFSET))
#endif	/* _ASMLANGUAGE */

/* SIO -- mpc860 serial channel chip -- register definitions */

/* Buffer Descriptor Pointer Definitions */

/* Receive BD status bits 16-bit value */

#define BD_RX_EMPTY_BIT		0x8000	/* buffer is empty */
#define BD_RX_WRAP_BIT		0x2000	/* last BD in chain */
#define BD_RX_INTERRUPT_BIT	0x1000	/* set interrupt when filled */
#define BD_RX_CON_MODE_BIT	0x0200	/* Continuous Mode bit */
#define BD_RX_IDLE_CLOSE_BIT	0x0100	/* Close on IDLE recv bit */
#define BD_RX_BREAK_CLOSE_BIT	0x0020	/* Close on break recv bit */
#define BD_RX_FRAME_CLOSE_BIT	0x0010	/* Close on frame error bit */
#define BD_RX_PARITY_ERROR_BIT	0x0008	/* Parity error in last byte */
#define BD_RX_OVERRUN_ERROR_BIT	0x0002	/* Overrun occurred */

/* Transmit BD status bits 16-bit value */

#define BD_TX_READY_BIT		0x8000	/* Transmit ready/busy bit */
#define BD_TX_WRAP_BIT		0x2000	/* last BD in chain */
#define BD_TX_INTERRUPT_BIT	0x1000	/* set interrupt when emptied */
#define BD_TX_CON_MODE_BIT	0x0200	/* Continuous Mode bit */
#define BD_TX_PREABMLE_BIT	0x0100	/* send preamble sequence */

#define BD_STATUS_OFFSET	0x00	/* two bytes */
#define BD_DATA_LENGTH_OFFSET	0x02	/* two bytes */
#define	BD_BUF_POINTER_OFFSET	0x04	/* four bytes */

/* SDMA Configuraton Register bit definition (SDCR - 0x30) */

#define SDCR_FRZ_MSK	0x00006000	/* Freeze mask */
#define SDCR_RAID_MSK	0x00000003	/* Risc Controller Arbitration ID */
#define SDCR_FAID_MSK   0x0000000c      /* FEC Arbitration ID mask */
#define SDCR_FAM_EN     0x00000040      /* FEC Agressive Mode Enable */
#define SDCR_FAID_BR6   0x00000000      /* FEC Arbitration ID U-Bus priority 6*/
#define SDCR_FAID_BR5   0x00000004      /* FEC Arbitration ID U-Bus priority 5*/
#define SDCR_FAID_BR2   0x00000008      /* FEC Arbitration ID U-Bus priority 2*/
#define SDCR_FAID_BR1   0x0000000c      /* FEC Arbitration ID U-Bus priority 1*/
#define SDCR_RAID_BR6	0x00000000	/* U-BUS arbitration priority 6 (BR6) */
#define SDCR_RAID_BR5	0x00000001	/* U-BUS arbitration priority 5 (BR5) */
#define SDCR_RAID_BR2	0x00000002	/* U-BUS arbitration priority 2 (BR2) */
#define SDCR_RAID_BR1	0x00000003	/* U-BUS arbitration priority 1 (BR1) */

/* SDMA Status Register bit definition (SDSR - 0x908) */

#define SDSR_SBER	0x80		/* Channel Bus Error */
#define SDSR_RINT	0x40		/* Reserved Interrupt */
#define SDSR_DSP2	0x02		/* DSP chain interrupt 2 */
#define SDSR_DSP1	0x01		/* DSP chain interrupt 1 */

/* IDMA Status Register bit definition (IDSR - 0x910) */

#define IDSR_OB		0x04		/* Out of Buffer */
#define IDSR_DONE	0x02		/* IDMA transfert Done */
#define IDSR_AD		0x01		/* Auxiliry Done */

/* Timer Global Configuration Register bit definition (TGCR - 0x980) */

#define TGCR_CAS4		0x8000		/* Cascade Timer 3 and 4 */
#define TGCR_FRZ4		0x4000		/* Freeze timer 4 */
#define TGCR_STP4		0x2000		/* Stop timer 4 */
#define TGCR_RST4		0x1000		/* Reset timer 4 */
#define TGCR_GM2		0x0800		/* Gate Mode for Pin 2 */
#define TGCR_FRZ3		0x0400		/* Freeze timer 3 */
#define TGCR_STP3		0x0200		/* Stop timer 3 */
#define TGCR_RST3		0x0100		/* Reset timer 3 */
#define TGCR_CAS2		0x0080		/* Cascade Timer 1 and 2 */
#define TGCR_FRZ2		0x0040		/* Freeze timer 2 */
#define TGCR_STP2		0x0020		/* Stop timer 2 */
#define TGCR_RST2		0x0010		/* Reset timer 2 */
#define TGCR_GM1		0x0008		/* Gate Mode for Pin 1 */
#define TGCR_FRZ1		0x0004		/* Freeze timer 1 */
#define TGCR_STP1		0x0002		/* Stop timer 1 */
#define TGCR_RST1		0x0001		/* Reset timer 1 */

/* Timer Mode Register bit definition (TMRx - 0x990) */

#define TMR_PS_MSK		0xff00	/* Prescaler Value */
#define TMR_CE_MSK		0x00c0	/* Capture Edge and Enable Interrupt */
#define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event */
#define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only */
#define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only */
#define TMR_CE_ANY		0x00c0	/* Capture on any TINx edge */
#define TMR_OM			0x0020	/* Output Mode */
#define TMR_ORI			0x0010	/* Output Reference Interrupt Enable */
#define TMR_FRR			0x0008	/* Free Run/Restart */
#define TMR_ICLK_MSK		0x0006	/* Timer Input Clock Source mask */
#define TMR_ICLK_IN_CAS		0x0000	/* Internally cascaded input */
#define TMR_ICLK_IN_GEN		0x0002	/* Internal General system clock */
#define TMR_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16 */
#define TMR_ICLK_TIN_PIN	0x0006	/* TINx pin */
#define TMR_GE			0x0001	/* Gate Enable */

/* Timer Event Register bit definition (TERx - 0x9B0) */

#define TER_REF		0x0002		/* Output Reference Event */
#define TER_CAP		0x0001		/* Capture Event */

/* BDG Configuratioon REgister bit definition (BRGC - 0x9F0) */

#define BRGC_RST		0x20000		/* Reset BRG */
#define BRGC_EN			0x10000		/* Enable BRG count */
#define BRGC_EXTC_MSK		0x08000		/* External Clock Source Mask */
#define BRGC_EXTC_BRGCLK	0x00000		/* Baud Rate Gen clock source */
#define BRGC_EXTC_CLK2 		0x04000		/* CLK2 pin = BRG source */
#define BRGC_EXTC_CLK6		0x08000		/* CLK6 pin = BRG source */
#define BRGC_ATB		0x02000		/* 1 = Autobaud on Rx */
						/* 0 = normal operation */
#define BRGC_CD_MSK		0x01FFE		/* clock divider 12 bit value */
#define BRGC_CD_SHIFT		0x1		/* shifted up one bit */
#define BRGC_DIV16		0x00001		/* BRG Clock divide by 16 */

/* UART Mode Register bit definition (PSMR - 0x0A08) */

#define PSMR_FLC		0x8000	/* Flow Control */
#define PSMR_SL			0x4000	/* Stop Length */
#define PSMR_CL_MSK		0x3000	/* Character Length Mask */
#define PSMR_CL_5_BITS		0x0000	/* Character Length: 5 bits */
#define PSMR_CL_6_BITS		0x1000	/* Character Length: 6 bits */
#define PSMR_CL_7_BITS		0x2000	/* Character Length: 7 bits */
#define PSMR_CL_8_BITS		0x3000	/* Character Length: 8 bits */
#define PSMR_UM_MSK		0x0c00	/* UART Mode Mask */
#define PSMR_UM_NORMAL		0x0000	/* UART Mode: normal */
#define PSMR_UM_NON_AUTO	0x0400	/* UART Mode: multidrop non-automatic */
#define PSMR_UM_AUTO		0x0c00	/* UART Mode: multidrop automatic */
#define PSMR_FRZ		0x0200	/* Freeze Transmission */
#define PSMR_RZS		0x0100	/* Receive Zero Stop bits */
#define PSMR_SYN		0x0080	/* Synchronous Mode */
#define PSMR_DRT		0x0040	/* Disable Receiver While Transmitting*/
#define PSMR_PEN		0x0010	/* Parity Enable */
#define PSMR_RPN_MSK		0x000c	/* Receiver Parity Mode Mask */
#define PSMR_RPN_ODD		0x0000	/* Receiver Parity Mode: Odd parity */
#define PSMR_RPN_LOW		0x0004	/* Receiver Parity Mode: Low parity */
#define PSMR_RPN_EVEN		0x0008	/* Receiver Parity Mode: Even parity */
#define PSMR_RPN_HIGH		0x000c	/* Receiver Parity Mode: High parity */
#define PSMR_TPN_MSK		0x0003	/* Transmitter Parity Mode Mask */
#define PSMR_TPN_ODD		0x0000	/* Transmit Parity Mode: Odd parity */
#define PSMR_TPN_LOW		0x0001	/* Transmit Parity Mode: Low parity */
#define PSMR_TPN_EVEN		0x0002	/* Transmit Parity Mode: Even parity */
#define PSMR_TPN_HIGH		0x0003	/* Transmit Parity Mode: High parity */

/* CPM - Communication Processor Module */

/* Command Register definitions (CPCR - 0x9C0) */    
 
#define CPM_CR_FLG              0x0001	/* flag - command executing */ 
#define	CPM_CR_RESET		0x8000	/* software reset command */
#define CPM_CR_OPCODE           0x0f00	/* command opcode */
#define	CPM_CR_CHAN(x)		(((x) & 0x000f) << 4)
#define	CPM_CR_OP(x)		(((x) & 0x000f) << 8)
    
/* CPCR - Channel Numbers */

#define CPM_CR_CHANNEL_SCC1     CPM_CR_CHAN(0x0)	/* SCC1 channel */ 
#define	CPM_CR_CHANNEL_I2C	CPM_CR_CHAN(0x1)	/* I2C channel */
#define CPM_CR_CHANNEL_SCC2     CPM_CR_CHAN(0x4)	/* SCC2 channel */
#define CPM_CR_CHANNEL_SPI      CPM_CR_CHAN(0x5)	/* SPI channel */ 
#define CPM_CR_CHANNEL_RTMR     CPM_CR_CHAN(0x5)	/* RISC timer channel */
#define CPM_CR_CHANNEL_SCC3     CPM_CR_CHAN(0x8)	/* SCC3 channel */ 
#define CPM_CR_CHANNEL_SMC1     CPM_CR_CHAN(0x9)	/* SMC1 channel */ 
#define CPM_CR_CHANNEL_IDMA1    CPM_CR_CHAN(0x1)	/* IDMA1 channel */ 
#define CPM_CR_CHANNEL_SCC4     CPM_CR_CHAN(0xc)	/* SCC4 channel */ 
#define CPM_CR_CHANNEL_SMC2     CPM_CR_CHAN(0xd)	/* SMC2 channel */ 
#define	CPM_CR_CHANNEL_PIP	CPM_CR_CHAN(0xd)	/* PIP channel */
#define CPM_CR_CHANNEL_IDMA2    CPM_CR_CHAN(0x5)	/* IDMA2 channel */ 
#define CPM_CR_CHANNEL_DSP1     CPM_CR_CHAN(0x9)	/* DSP1 channel */ 
#define CPM_CR_CHANNEL_DSP2     CPM_CR_CHAN(0xd)	/* DSP2 channel */ 
 
/* CPCR - opcodes */
 
#define CPM_CR_OPCODE_INIT_RT   CPM_CR_OP(0x0)		/* Init rx and tx */
#define CPM_CR_OPCODE_INIT_R    CPM_CR_OP(0x1)		/* init rx only */
#define CPM_CR_OPCODE_INIT_T    CPM_CR_OP(0x2)		/* init tx only */
#define CPM_CR_OPCODE_HUNT      CPM_CR_OP(0x3)		/* rx frame hunt mode */
#define CPM_CR_OPCODE_STOP      CPM_CR_OP(0x4)		/* stop tx */
#define CPM_CR_OPCODE_GRSTOP    CPM_CR_OP(0x5)		/* gracefully stop tx */
#define	CPM_CR_OPCODE_IDMA_INIT	CPM_CR_OP(0x5)		/* init idma */
#define CPM_CR_OPCODE_RESTART   CPM_CR_OP(0x6)		/* restart tx */
#define CPM_CR_OPCODE_CLOSE     CPM_CR_OP(0x7)		/* close rx buffer */
#define CPM_CR_OPCODE_SET_GROUP CPM_CR_OP(0x8)		/* set group address */
#define	CPM_CR_OPCODE_SET_ITMR	CPM_CR_OP(0x8)		/* set itimer */
#define	CPM_CR_OPCODE_GCI_TMO	CPM_CR_OP(0x9)		/* gci timeout */
#define CPM_CR_OPCODE_RESET_BCS CPM_CR_OP(0xa)		/* blk chk seq reset */
#define	CPM_CR_OPCODE_GCI_ABRT	CPM_CR_OP(0xa)		/* gci abort request */
#define	CPM_CR_OPCODE_IDMA_STOP	CPM_CR_OP(0xb)		/* stop idma */
#define	CPM_CR_OPCODE_DSP_START	CPM_CR_OP(0xc)		/* start DSP */
#define	CPM_CR_OPCODE_DSP_INIT	CPM_CR_OP(0xd)		/* init DSP */    

#define CPM_CR_SCC_INIT_RT      CPM_CR_OPCODE_INIT_RT	/* rx and tx init */
#define CPM_CR_SCC_INIT_R       CPM_CR_OPCODE_INIT_R	/* init rx only */
#define CPM_CR_SCC_INIT_T       CPM_CR_OPCODE_INIT_T	/* init tx only */
#define CPM_CR_SCC_HUNT         CPM_CR_OPCODE_HUNT	/* rx frm hunt mode */
#define CPM_CR_SCC_STOP         CPM_CR_OPCODE_STOP	/* stop tx */
#define CPM_CR_SCC_GRSTOP       CPM_CR_OPCODE_GRSTOP	/* graceful stop tx */
#define CPM_CR_SCC_RESTART      CPM_CR_OPCODE_RESTART	/* restart tx */
#define CPM_CR_SCC_CLOSE        CPM_CR_OPCODE_CLOSE	/* close rx buffer */
#define CPM_CR_SCC_SET_GROUP    CPM_CR_OPCODE_SET_GROUP	/* set group adrs */
#define CPM_CR_SCC_RESET_BCS    CPM_CR_OPCODE_RESET_BCS	/* reset BCS */
 
#define CPM_CR_SMC_INIT_RT      CPM_CR_OPCODE_INIT_RT	/* rx and tx init */
#define CPM_CR_SMC_INIT_R       CPM_CR_OPCODE_INIT_R	/* init rx only */
#define CPM_CR_SMC_INIT_T       CPM_CR_OPCODE_INIT_T	/* init tx only */
#define CPM_CR_SMC_HUNT         CPM_CR_OPCODE_HUNT	/* rx frm hunt mode */
#define CPM_CR_SMC_STOP         CPM_CR_OPCODE_STOP	/* stop tx */
#define CPM_CR_SMC_RESTART	CPM_CR_OPCODE_RESTART	/* restart tx */
#define CPM_CR_SMC_CLOSE        CPM_CR_OPCODE_CLOSE	/* close rx buffer */

#define CPM_CR_SMC_GCI_INIT_RT	CPM_CR_OPCODE_INIT_RT	/* rx and tx init */
#define CPM_CR_SMC_GCI_TMO	CPM_CR_OPCODE_GCI_TMO	/* GCI timeout */
#define CPM_CR_SMC_GCI_ABORT    CPM_CR_OPCODE_GCI_ABRT	/* GCI abort */

#define CPM_CR_SPI_INIT_RT      CPM_CR_OPCODE_INIT_RT	/* rx and tx init */
#define CPM_CR_SPI_INIT_R       CPM_CR_OPCODE_INIT_R	/* init rx only */
#define CPM_CR_SPI_INIT_T       CPM_CR_OPCODE_INIT_T	/* init tx only */