📄 f06x_sar16data.lst
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192 {
193 1 char old_SFRPAGE = SFRPAGE;
194 1
195 1 SFRPAGE = UART0_PAGE; // Switch to UART0 page
196 1
197 1 SCON0 = 0x50; // SCON: mode 1, 8-bit UART, enable RX
198 1 SSTA0 = 0x10; // Timer 1 generates UART0 baud rate and
199 1 // UART0 baud rate divide by two disabled
200 1
201 1 SFRPAGE = TIMER01_PAGE; // Switch to Timer 0/1 page
202 1
203 1 TMOD = 0x20; // TMOD: timer 1, mode 2, 8-bit reload
204 1 TH1 = -(SYSCLK/BAUDRATE/16); // set Timer1 reload value for baudrate
205 1 TR1 = 1; // start Timer1
206 1 CKCON |= 0x10; // Timer1 uses SYSCLK as time base
207 1 PCON |= 0x80; // SMOD = 1
208 1
209 1 SFRPAGE = UART0_PAGE; // Switch to UART0 page
210 1
211 1 TI0 = 1; // Indicate TX ready
212 1
213 1 SFRPAGE = old_SFRPAGE; // restore SFRPAGE
214 1
215 1 }
216
217 //-----------------------------------------------------------------------------
218 // SYSCLK_Init
219 //-----------------------------------------------------------------------------
220 void SYSCLK_Init (void)
221 {
222 1 char old_SFRPAGE = SFRPAGE;
223 1 int i;
224 1
225 1 SFRPAGE = CONFIG_PAGE; // Switch to Configuration Page
226 1
227 1 OSCXCN = 0x67; // start external oscillator with
228 1 // 22.1184MHz crystal on TB
229 1
230 1 for (i=0; i <5000; i++) ; // XTLVLD blanking interval (>1ms)
231 1
232 1 while (!(OSCXCN & 0x80)) ; // Wait for crystal osc. to settle
233 1
234 1 RSTSRC = 0x04; // enable missing clock detector reset
235 1
236 1 CLKSEL = 0x01; // change to external crystal
237 1
238 1 OSCICN = 0x00; // disable internal oscillator
239 1
240 1
241 1
C51 COMPILER V8.08 F06X_SAR16DATA 02/15/2008 14:18:26 PAGE 5
242 1 SFRPAGE = old_SFRPAGE; // restore SFRPAGE
243 1 }
244
245 //-----------------------------------------------------------------------------
246 // ADC0_Init
247 //-----------------------------------------------------------------------------
248 void ADC0_Init (void)
249 {
250 1 char old_SFRPAGE = SFRPAGE;
251 1 int i;
252 1
253 1 SFRPAGE = ADC0_PAGE; // Switch to ADC0 Page
254 1
255 1 ADC0CN = 0x44; // ADC Disabled, Timer3 start-of-conversion
256 1 // track 16 SAR clocks before data conversion
257 1 // upon Timer3 OV. DMA will enable ADC as needed
258 1 //
259 1
260 1 REF0CN = 0x03; // turn on bias generator and internal reference.
261 1
262 1 for(i=0;i<10000;i++); // Wait for Vref to settle (large cap used on target board)
263 1
264 1 AMX0SL = 0x00; // Single-ended mode
265 1
266 1 ADC0CF = (SYSCLK/25000000) << 4; // Select SAR clock frequency =~ 25MHz
267 1
268 1 SFRPAGE = old_SFRPAGE; // restore SFRPAGE
269 1 }
270
271
272
273 //-----------------------------------------------------------------------------
274 // DMA0_Init
275 //-----------------------------------------------------------------------------
276 void DMA0_Init (void)
277 {
278 1 char old_SFRPAGE = SFRPAGE;
279 1
280 1 SFRPAGE = DMA0_PAGE; // Switch to DMA0 Page
281 1
282 1 DMA0CN = 0x00; // Disable DMA interface
283 1
284 1 DMA0DA = XRAM_START_ADD; // Starting Point for XRAM addressing
285 1
286 1 DMA0CT = NUM_SAMPLES; // Get NUM_SAMPLES samples
287 1
288 1 DMA0IPT = 0x00; // Start writing at location 0
289 1
290 1 // Push instructions onto stack in order they will be executed
291 1 DMA0IDT = DMA0_GET_ADC0; // DMA to move ADC0 data.
292 1 DMA0IDT = DMA0_END_OF_OP;
293 1
294 1 DMA0BND = 0x00; // Begin instruction executions at address 0
295 1 DMA0CN = 0xA0; // Mode 1 Operations, Begin Executing DMA Ops
296 1 // (which will start ADC0)
297 1
298 1 SFRPAGE = old_SFRPAGE; // restore SFRPAGE
299 1 }
300
301 //------------------------------------------------------------------------------------
302 // Timer3_Init
303 //------------------------------------------------------------------------------------
C51 COMPILER V8.08 F06X_SAR16DATA 02/15/2008 14:18:26 PAGE 6
304 //
305 // Configure Timer3 to auto-reload and generate ADC sample rate
306 // specified by <counts> using SYSCLK as its time base.
307 //
308 void Timer3_Init (int counts)
309 {
310 1 char old_SFRPAGE = SFRPAGE;
311 1
312 1 SFRPAGE = TMR3_PAGE; // Switch to Timer 3 page
313 1
314 1 TMR3CN = 0x00; // Stop Timer3; Clear TF3;
315 1 TMR3CF = 0x08; // use SYSCLK as timebase
316 1 RCAP3 = -counts; // Init reload values
317 1 TMR3 = 0xffff; // set to reload immediately
318 1 TR3 = 1; // start Timer3
319 1
320 1 SFRPAGE = old_SFRPAGE; // restore SFRPAGE
321 1 }
322
323 //-----------------------------------------------------------------------------
324 // EMIF_Init
325 //-----------------------------------------------------------------------------
326 //
327 // Configure the external memory interface to use upper port pins in
328 // non-multiplexed mode to a mixed on-chip/off-chip configuration without
329 // Bank Select.
330 //
331 void EMIF_Init (void)
332 {
333 1 char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
334 1
335 1 SFRPAGE = EMI0_PAGE; // Save SFR_PAGE
336 1 EMI0CF = 0x3C; // upper ports; non-muxed mode;
337 1 // split mode w/o bank select
338 1 EMI0TC = 0x45; // timing (7-cycle MOVX)
339 1
340 1 SFRPAGE = CONFIG_PAGE;
341 1 P4MDOUT |= 0xFF; // all EMIF pins configured as
342 1 P5MDOUT |= 0xFF; // push-pull
343 1 P6MDOUT |= 0xFF;
344 1 P7MDOUT |= 0xFF;
345 1
346 1 SFRPAGE = SFRPAGE_SAVE; // restore SFR_PAGE
347 1 }
348
349 //-----------------------------------------------------------------------------
350 // SendData
351 //-----------------------------------------------------------------------------
352 //
353 //Send data out UART0
354 //
355 void SendData(void)
356 {
357 1 unsigned int i;
358 1 char old_SFRPAGE = SFRPAGE;
359 1 SFRPAGE = UART0_PAGE; // Switch to UART0 page
360 1
361 1 read_ptr = XRAM_START_ADD; // Set pointer to beginning of data
362 1
363 1 for (i=0;i<NUM_SAMPLES;i++)
364 1 {
365 2 printf ("%u\n",*read_ptr); // Send data as unsigned integers
C51 COMPILER V8.08 F06X_SAR16DATA 02/15/2008 14:18:26 PAGE 7
366 2 read_ptr++;
367 2 }
368 1
369 1 SFRPAGE = old_SFRPAGE;
370 1
371 1 }//End
372
373
374
375
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 361 ----
CONSTANT SIZE = 111 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 3 3
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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