test_compact_flash.v

基于 MAXII CPLD的对Compact_Flash的读写

 /******************************************************************************************
  TEST BENCH FOR COMPACT FLASH
  March 2007
  ******************************************************************************************/
module test_compact_flash;            
	   wire[10:0] t_host_address;
		wire [1:0] t_ce_1;
		wire t_we;
		wire t_reg_1;
		wire t_iord;
		wire t_iowr;
		wire t1_reset;
		wire t_oe;
		wire t_h_int;
		wire t_h_ready;
     	wire temp;
		
		reg t_h_enable;
		reg t_h_iom;
		reg [10:0]t_h_address;
		reg t_ireq;
		reg t_ready;
		reg [1:0] t_reset;
		reg [3:0] t_h_control;
		reg [1:0] t_cd_1=2'b00;
		reg clk;
		
		/***************************************************************************************************
		Instantiating the block
		****************************************************************************************************/
		compact_flash u0(.h_ack(clk),.host_address(t_host_address),.ce_1(t_ce_1),.we(t_we),.reg_1(t_reg_1),
                       .iord(t_iord),.iowr(t_iowr),.reset(t1_reset),.oe(t_oe),.h_int(t_h_int),.cd_1(t_cd_1), .h_enable(t_h_enable),
		                 .h_address(t_h_address),.ready(t_ready),.h_control(t_h_control),.h_iom(t_h_iom),.h_reset(t_reset),.ireq(t_ireq),.h_ready(t_h_ready));                    

//Generation of clock for use in Acknowledgement signal

initial 
     begin
        clk=0;
     forever #10 clk = ~clk;
         end
   
assign temp=((~temp)&(t_h_int)&(t_h_enable))?1'b1:1'b0;                     

//Generating control signals

always 
    begin
            t_h_address=11'b01000011110;  
            t_h_iom=1'b0;
        #10 t_h_control=4'b0000;
            t_ready=1'b1;
        #20 t_h_control=4'b0001;
        #20 t_h_control=4'b0010;
        #20 t_h_control=4'b0011;
        #20 t_h_control=4'b0100;
        #20 t_h_control=4'b0101;
        #20 t_h_control=4'b0110;
        #20 t_h_control=4'b0111;
        #20 t_h_control=4'b1100;
        #20 t_h_control=4'b1000;
        #20 t_h_control=4'b1001;
        #20 t_h_control=4'b1010;
        #20 t_h_control=4'b1011;
        #20 t_h_control=4'b0000;
            t_h_iom=1'b1;
            t_ireq=1'b1;
        #20 t_h_control=4'b0001;
        #20 t_h_control=4'b0010;
        #20 t_h_control=4'b0011;
        #20 t_h_control=4'b0100;
        #20 t_h_control=4'b0101;
        #20 t_h_control=4'b0110;
        #20 t_h_control=4'b0111;
        #20 t_h_control=4'b1000;
        #20 t_h_control=4'b1001;
        #20 t_h_control=4'b1010;
        #20 t_h_control=4'b0000;
           end
           
 always @(posedge clk)      begin     //As long as acknowledgement signal is high the process continues
   #2   if (t_reset==2'b11)   begin   //Hardware reset,so the acknowledgement is made low  
          if((t1_reset==1'b1)&(t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:5]==6'b111111)&(t_host_address[4:0]==5'b00000)&(t_h_int==1'b0))                          
              $display("Hardware reset is asserted");
           else 
              $display("Hardware reset is not asserted");
                                end               
                        
         if(t_h_iom==1'b0)                          begin                              //Checking for memory mode
          if(t_h_ready==1'b1)                       begin 
           if(t_h_control==4'b0000)                 begin                     //Configuration option register read
            if((t_ce_1===2'bx0)&&(t_reg_1==1'b0)&&(t_oe==1'b0)&&(t_we==1'b1)&&(t_host_address[10:5]===6'bxxxxxx)&&(t_host_address[4:0]==5'b00000))
              $display("Configuration Option Register Read Verified", $time);
                else                   
                   $display("Error", $time);
                     end
                                                    
        if((t_h_control==4'b0001)&(t_reset=2'b00)) begin          //Configuration option register write
          if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b00000)&(t_h_int==1'b0)) 
             $display("Software reset is asserted", $time);
              else 
                $display("Software reset is not asserted", $time);
             end
                  
         if(t_h_control==4'b0001)begin
          if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b00000))
               $display("Configuration Option Register Write Verified", $time);
               else
                   $display("Error",$time);
                end      
                  // end  
         
         if(t_h_control==4'b0010)        begin                   //Card status register read
          if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b00010))
             $display("Card Status Register Read Verified",$time);
              else 
                  $display("Error",$time);
                   
                       end
                           
          if(t_h_control==4'b0011)         begin                   //Card status register write 
           if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b00010))
             $display("Card Status Register Write Verified",$time);
             else 
                  $display("Error",$time);
                  
                       end
                        
          if(t_h_control==4'b0100)          begin                  //Pin replacement register read
           if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b00100))
            $display("Pin Replacement Register Read Verified",$time);
            else
                  $display("Error",$time);
                   
                       end

          if(t_h_control==4'b0101)           begin                 //Pin replacement register write
           if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b00100))
             $display("Pin Replacement Register Write Verified",$time);
             else 
                  $display("Error",$time);
                  
                       end
                         
          if(t_h_control==4'b0110)           begin                //Common memory read (8 bit D7-d0)
           if((t_ce_1==2'b10)&(t_reg_1==1'b1)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:0]===t_h_address[10:0]))
             $display("Common Memory Read (8 bit D7-d0) Verified",$time);
              else
                 $display("Error",$time);
                  
                      end
                                                    
          if(t_h_control==4'b0111)              begin               //Common memory read (8 bit D15-D8)
           if((t_ce_1==2'b01)&(t_reg_1==1'b1)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:0]===t_h_address[10:0]))
            $display("Common Memory Read (8 bit D15-D8) Verified",$time);
              else 
              $display("Error",$time);
                    
                       end
                                                     
          if(t_h_control==4'b1100)              begin               //Common memory read (16 bit D15-D0)
           if((t_ce_1==2'b00)&(t_reg_1==1'b1)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:1]===t_h_address[10:1])&(t_host_address[0]===1'b0))
            $display("Common Memory Read (16 bit D15-D0) Verified",$time);
              else 
              $display("Error",$time);
                    
                       end
                                                
          if(t_h_control==4'b1000)           begin                //Common memory write(8 bit D7-D0)
           if((t_ce_1==2'b10)&(t_reg_1==1'b1)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:0]===t_h_address[10:0]))
             $display("Common Memory Write (8 bit D7-D0) Verified",$time);
             else 
                  $display("Error",$time);
                   
                       end
                                   
          if(t_h_control==4'b1001)           begin                //Common memory write(8 bit D15-D8)
           if((t_ce_1==2'b01)&(t_reg_1==1'b1)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:0]===t_h_address[10:0]))
            $display("Common Memory Write(8 bit D15-D8) Verified",$time);
              else
                  $display("Error",$time);
                  
                       end
                                                      
          if(t_h_control==4'b1010)            begin               //Common memory write(16 bit D15-D0)  
           if((t_ce_1==2'b00)&(t_reg_1==1'b1)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:1]===t_h_address[10:1])&(t_host_address[0]==1'b0))
             $display("Common Memory Write(16 bit D15-D0) Verified",$time);
             else 
                  $display("Error",$time);
                   
                       end
                                    
          if(t_h_control==4'b1011)            begin               //Card information structure read
           if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:1]===10'bxxxxxxxxxx)&(t_host_address[0]==1'b0))
             $display("Card Information Structure Read Verified",$time);
             else 
                  $display("Error",$time);
                    
                       end
                        end
                        end                             
 //Testing of I/O funstions
         
          if((t_h_iom==1'b1)||(t_ireq==1'b1)) begin
            if(t_h_control==4'b0000)            begin             //Checking for I/O mode
              if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b01010))
                $display("I/O Base 0 Register Verified",$time);
                else 
                  $display("Error",$time);
                      end
                  
          if(t_h_control==4'b0001)           begin             //I/O base 1 register  
           if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b0)&(t_we==1'b1)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b01100))
              $display("I/O Base 1 Register Verified",$time);
              else 
                  $display("Error",$time);
                    end
                          
          if(t_h_control==4'b0010)           begin             //I/O limit  
           if((t_ce_1===2'bx0)&(t_reg_1==1'b0)&(t_oe==1'b1)&(t_we==1'b0)&(t_host_address[10:5]===6'bxxxxxx)&(t_host_address[4:0]==5'b10010))
             $display("I/O Limit Verified",$time);
              else 
                  $display("Error",$time);
                   
                       end
          
          if(t_h_control==4'b0011)          begin            //I/O mode single byte input access (8 bits) 
           if((t_ce_1==2'b10)&(t_reg_1==1'b0)&(t_iord==1'b0)&(t_iowr==1'b1)&(t_host_address[0]==1'b0))
             $display("I/O Mode Single Byte Input Access (8 bits) Verified",$time);
             else 
                  $display("Error",$time);
                           end
          
          if(t_h_control==4'b0100)          begin            //I/O mode single byte output access (8 bits)
           if((t_ce_1==2'b10)&(t_reg_1==1'b0)&(t_iord==1'b1)&(t_iowr==1'b0)&(t_host_address[0]==1'b0))
             $display("I/O Mode Single Byte Output Access (8 bits) Verified",$time);
             else 
              $display("Error",$time);
                        end
                
          if(t_h_control==4'b0101)          begin            //I/O mode word input access (16 bits)   
           if((t_ce_1==2'b00)&(t_reg_1==1'b0)&(t_iord==1'b0)&(t_iowr==1'b1)&(t_host_address[0]==1'b0))
            $display("I/O Mode Single Byte Output Access (8 bits) Verified",$time);
              else 
            $display("Error",$time);
                      end
                
          if(t_h_control==4'b0110)          begin            //I/O mode word output access (16 bits)
           if((t_ce_1==2'b00)&(t_reg_1==1'b0)&(t_iord==1'b1)&(t_iowr==1'b0)&(t_host_address[0]==1'b0))
             $display("I/O Mode Word Output Access (16 bits) Verified",$time);
             else 
             $display("Error",$time);
                            end
              
          if(t_h_control==4'b0111)          begin            //I/O read inhibit  
           if((t_ce_1===2'bxx)&(t_reg_1==1'b1)&(t_iord==1'b0)&(t_iowr==1'b1)&(t_host_address[0]===1'bx))
             $display("I/O Read Inhibit Verified",$time);
              else 
             $display("Error",$time);
                            end
                     
          if(t_h_control==4'b1000)           begin           //I/O write inhibit  
           if((t_ce_1===2'bxx)&(t_reg_1==1'b1)&(t_iord==1'b1)&(t_iowr==1'b0)&(t_host_address[0]===1'bx))
             $display("I/O Write Inhibit Verified",$time);
            else 
             $display("Error",$time);
                      end
                     
           if(t_h_control==4'b1001)             begin          //High byte input only
            if((t_ce_1==2'b10)&(t_reg_1==1'b0)&(t_iord==1'b0)&(t_iowr==1'b1)&(t_host_address[0]===1'bx))
             $display("High Byte Input Only Verified",$time);
           else 
             $display("Error",$time);
                      end
                                     
           if(t_h_control==4'b1010)             begin          //High byte output only 
            if((t_ce_1==2'b10)&(t_reg_1==1'b0)&(t_iord==1'b1)&(t_iowr==1'b0)&(t_host_address[0]===1'bx))
              $display("High Byte Output Only Verified",$time);
              else 
                   $display("Error",$time);
                      end
                            end
                                 end 
  initial
   #490 $finish;

                  endmodule