upcount_2.v

来自「基于 MAXII 的CPLD 对mobil dram 的读写操作」· Verilog 代码 · 共 22 行

/***************************************************************************************************************
* TWO BIT UPCOUNTER
***************************************************************************************************************/

module upcount_2( clk, reset, count_en, count);
input clk;                    //clk of the processer used
input reset;                  //asychronous reset
input count_en;               
output [1:0] count;             
reg [1:0] count;             
always @ (posedge reset,posedge clk) begin
    if (reset == 1)
        count = 2'b00;
    else 
	if(count_en==1)
        count = count + 2'b01;
end


endmodule

/******************************************* END MODULE *****************************************************/